4 POWER SUPPLY
S1C17624/604/622/602/621 TECHNICAL MANUAL
Seiko Epson Corporation
4-3
Condition Control bits
Operating mode V
DD LCD driver VD1MD VCSEL DSPC[1:0]
Flash erase/
programming
mode 1
1.8 to 2.7 V – (Not supported)
2.7 to 3.6 V Used 1 1 Other than 0x0
Not used 1 0 0x0
For the DSPC[1:0] settings, see “LCD Display Control Register (LCD_DCTL)” in the “LCD Driver (LCD)”
chapter.
Heavy Load Protection Function4.5
In order to ensure a stable circuit behavior and LCD display quality even if the power supply voltage fluctuates due
to driving an external load, the internal logic voltage regulator and the LCD system voltage regulator have a heavy
load protection function.
The internal logic voltage regulator enters heavy load protection mode by writing 1 to the HVLD/VD1_CTL regis-
ter and it ensures stable V
D1 output.
V
D1 may become unstable in the operations shown below and in other conditions. If the IC operations are unstable
due to these conditions during evaluation, set the internal logic voltage regulator to heavy load protection mode be-
fore starting the operations.
• When driving a diode or buzzer in which a large current flows using a port output (Maintain the regulator in
heavy load protection mode while the port is driving the load.)
• When switching the system clock from the high
-speed clock to the low-speed clock and vice versa (Set the regu-
lator in heavy load protection mode immediately before switching the clock and maintain it for several 10 µs
after the switching has completed.)
• When turning the high-speed oscillator (OSC3, IOSC) on (Set the regulator in heavy load protection mode im-
mediately before turning the oscillator on and maintain it until the oscillation s
tabilization wait time has elapsed.)
• When placing/releasing the system into/from HALT/SLEEP mode at frequent intervals (Maintain the regulator in
heavy load protection mode while the processing is being repeated.)
The LCD system voltage regulator enters heavy load protection mode by writing 1 to the LHVLD/LCD_VREG
register and it ensures stable V
C1–VC3 outputs. Use the heavy load protection function when the LCD display has
inconsistencies in density.
Note: Current consumption increases in heavy load protection mode, therefore do not set heavy load
protection mode with software if unnecessary.
Control Register Details4.6
6.1 List of Power Control RegistersTable 4.
Address Register name Function
0x5120 VD1_CTL VD1 Control Register Controls the VD1 voltage and heavy load protection mode.
0x50a3 LCD_VREG LCD Voltage Regulator Control Register Controls the LCD drive voltage regulator.
The power control registers are described in detail below. These are all 8-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
VD1 Control Register (VD1_CTL)
Register name Address Bit Name Function Setting Init. R/W Remarks
VD1 Control
Register
(VD1_CTL)
0x5120
(8 bits)
D7–6
–
reserved – – – 0 when being read.
D5
HVLD
V
D1 heavy load protection mode 1 On 0 Off 0 R/W
D4–1
–
reserved – – – 0 when being read.
D0
VD1MD
Flash erase/programming mode 1
Flash (2.5 V)
0
Norm.(1.8 V)
0 R/W
D[7:6] Reserved
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