Epson S1C17624 - I2 C Slave Address Setup Register (I2 CS_SADRS); I2 C Slave Control Register (I2 CS_CTL)

21 I
2
C SLAVE (I2CS)
S1C17624/604/622/602/621 TECHNICAL MANUAL Seiko Epson Corporation
21-11
I
2
C Slave Address Setup Register (I2CS_SADRS)
Register name Address Bit Name Function Setting Init. R/W Remarks
I
2
C Slave
Address Setup
Register
(I2CS_SADRS)
0x4364
(16 bits)
D15–7
–
reserved – – – 0 when being read.
D6–0
SADRS[6:0]
I
2
C slave address 0–0x7f 0x0 R/W
D[15:7] Reserved
D[6:0] SADRS[6:0]: I2CS Address Bits
Sets the slave address of the I2CS module to this register. (Default: 0x0)
I
2
C Slave Control Register (I2CS_CTL)
Register name Address Bit Name Function Setting Init. R/W Remarks
I
2
C Slave
Control Register
(I2CS_CTL)
0x4366
(16 bits)
D15–9
–
reserved – – – 0 when being read.
D8
TBUF_CLR
I2CS_TRNS register clear 1 Clear state 0 Normal 0 R/W
D7
I2CSEN
I
2
C slave enable 1 Enable 0 Disable 0 R/W
D6
SOFTRESET
Software reset 1 Reset 0 Cancel 0 R/W
D5
NAK_ANS
NAK answer 1 NAK 0 ACK 0 R/W
D4
BFREQ_EN
Bus free request enable 1 Enable 0 Disable 0 R/W
D3
CLKSTR_EN
Clock stretch On/Off 1 On 0 Off 0 R/W
D2
NF_EN
Noise filter On/Off 1 On 0 Off 0 R/W
D1
ASDET_EN
Async.address detection On/Off 1 On 0 Off 0 R/W
D0
COM_MODE
I
2
C slave communication mode 1 Active 0 Standby 0 R/W
D[15:9] Reserved
D8 TBUF_CLR: I2CS_TRNS Register Clear Bit
Clears the I2CS_TRNS register.
1 (R/W): Clear state
0 (R/W): Normal state (clear state cancellation) (default)
When TBUF_CLR is set to 1, the I2CS_TRNS register enters clear state. After that writing 0 to TBUF_
CLR returns the I2CS_TRNS register to normal state. It is not necessary to insert a waiting time be-
tween writing 1 and 0.
If a new transmission is started when the I2CS_TRNS register
still stores data for the previous trans-
mission that has already finished, the data will be sent when TXEMP/I2CS_ASTAT register is set. In
order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR before starting transmis-
sion (before slave selection). The clear operation is not required if transmit data is written to the I2CS_
TRNS register before TXEMP is set to 1.
Data can be wr
itten to the I2CS_TRNS register even if it is placed into clear state (TBUF_CLR = 1).
However, this writing does not reset TXEMP to 0. Note that TXEMP is not reset to 0 when TBUF_CLR
is set back to 0. Therefore, data must be written to the I2CS_TRNS register when TBUF_CLR = 0.
D7 I2CSEN: I
2
C Slave Enable Bit
Enables or disables operations of the I2CS module.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When I2CSEN is set to 1
, the I2CS module is activated and data transfer is enabled.
When I2CSEN is set to 0, the I2CS module goes off.
D6 SOFTRESET: Software Reset Bit
Resets the I2CS module.
1 (R/W): Reset
0 (R/W): Cancel reset state (default)
To reset the I2CS module, write 1 to SOFTRESET to place the I2CS module into reset status, then
write 0 to SOFTRESET to release it from reset status. It is not necessary to insert a waiting time be-
tween writin
g 1 and 0. The I2CS module initializes the I
2
C communication process and put the SDA1
and SCL1 pins into high-impedance to be ready to detect a start condition. Furthermore, the I2CS con-
trol bits except for SOFTRESET are initialized. Perform the software reset in the initial setting process
before staring communication.