Epson S1C17624 - 0 x4280-0 x4288 Fine Mode 8-bit Timer Ch.1; 0 x4306-0 x4318 Interrupt Controller

APPENDIX A LIST OF I/O REGISTERS
S1C17624/604/622/602/621 TECHNICAL MANUAL Seiko Epson Corporation
AP-A-9
0x4280–0x4288 Fine Mode 8-bit Timer Ch.1
Register name Address Bit Name Function Setting Init. R/W Remarks
T8F Ch.1
Count Clock
Select Register
(T8F_CLK1)
0x4280
(16 bits)
D15–4
–
reserved – – – 0 when being read.
D3–0
DF[3:0]
Count clock division ratio select DF[3:0] Division ratio 0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
T8F Ch.1
Reload Data
Register
(T8F_TR1)
0x4282
(16 bits)
D15–8
–
reserved – – – 0 when being read.
D7–0
TR[7:0]
Reload data
TR7 = MSB
TR0 = LSB
0x0 to 0xff 0x0 R/W
T8F Ch.1
Counter Data
Register
(T8F_TC1)
0x4284
(16 bits)
D15–8
–
reserved – – – 0 when being read.
D7–0
TC[7:0]
Counter data
TC7 = MSB
TC0 = LSB
0x0 to 0xff 0xff R
T8F Ch.1
Control Register
(T8F_CTL1)
0x4286
(16 bits)
D15–12
–
reserved – – – 0 when being read.
D11–8
TFMD[3:0]
Fine mode setup 0x0 to 0xf 0x0 R/W
Set a number of times
to insert delay into a
16-underflow period.
D7–5
–
reserved – – – 0 when being read.
D4
TRMD
Count mode select 1 One shot 0 Repeat 0 R/W
D3–2
–
reserved – – – 0 when being read.
D1
PRESER
Timer reset 1 Reset 0 Ignored 0 W
D0
PRUN
Timer run/stop control 1 Run 0 Stop 0 R/W
T8F Ch.1
Interrupt
Control Register
(T8F_INT1)
0x4288
(16 bits)
D15–9
–
reserved – – – 0 when being read.
D8
T8FIE
T8F interrupt enable 1 Enable 0 Disable 0 R/W
D7–1
–
reserved – – – 0 when being read.
D0
T8FIF
T8F interrupt flag 1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0 R/W Reset by writing 1.
0x4306–0x4318 Interrupt Controller
Register name Address Bit Name Function Setting Init. R/W Remarks
Interrupt Level
Setup Register 0
(ITC_LV0)
0x4306
(16 bits)
D15–11
–
reserved – – – 0 when being read.
D10–8
ILV1[2:0]
P1 interrupt level 0 to 7 0x0 R/W
D7–3
–
reserved – – – 0 when being read.
D2–0
ILV0[2:0]
P0 interrupt level 0 to 7 0x0 R/W
Interrupt Level
Setup Register 1
(ITC_LV1)
0x4308
(16 bits)
D15–11
–
reserved – – – 0 when being read.
D10–8
ILV3[2:0]
CT/RTC interrupt level 0 to 7 0x0 R/W
D7–3
–
reserved – – – 0 when being read.
D2–0
ILV2[2:0]
SWT interrupt level 0 to 7 0x0 R/W
Interrupt Level
Setup Register 2
(ITC_LV2)
0x430a
(16 bits)
D15–11
–
reserved – – – 0 when being read.
D10–8
ILV5[2:0]
SVD interrupt level 0 to 7 0x0 R/W
D7–3
–
reserved – – – 0 when being read.
D2–0
ILV4[2:0]
T8OSC1 interrupt level 0 to 7 0x0 R/W
Interrupt Level
Setup Register 3
(ITC_LV3)
0x430c
(16 bits)
D15–11
–
reserved – – – 0 when being read.
D10–8
ILV7[2:0]
T16E Ch.0 interrupt level 0 to 7 0x0 R/W
D7–3
–
reserved – – – 0 when being read.
D2–0
ILV6[2:0]
LCD/T16A2 Ch.0 interrupt level 0 to 7 0x0 R/W
Interrupt Level
Setup Register 4
(ITC_LV4)
0x430e
(16 bits)
D15–11
–
reserved – – – 0 when being read.
D10–8
ILV9[2:0]
T16 Ch.0 interrupt level 0 to 7 0x0 R/W
D7–3
–
reserved – – – 0 when being read.
D2–0
ILV8[2:0]
T8F Ch.0/Ch.1 interrupt level 0 to 7 0x0 R/W
Interrupt Level
Setup Register 5
(ITC_LV5)
0x4310
(16 bits)
D15–11
–
reserved – – – 0 when being read.
D10–8
ILV11[2:0]
T16 Ch.2 interrupt level 0 to 7 0x0 R/W
D7–3
–
reserved – – – 0 when being read.
D2–0
ILV10[2:0]
T16 Ch.1 interrupt level 0 to 7 0x0 R/W