Epson S1C17624 - RFC Time Base Counter Low and High Registers (RFC_TCL, RFC_TCH); RFC Interrupt Mask Register (RFC_IMSK)

25 R/F CONVERTER (RFC)
25-12
Seiko Epson Corporation S1C17624/604/622/602/621 TECHNICAL MANUAL
RFC Time Base Counter Low and High Registers (RFC_TCL, RFC_TCH)
Register name Address Bit Name Function Setting Init. R/W Remarks
RFC Time Base
Counter Low
Register
(RFC_TCL)
0x53a8
(16 bits)
D15–0
TC[15:0]
Time base counter low-order 16-
bit data
0x0–0xffff 0x0 R/W
RFC Time Base
Counter High
Register
(RFC_TCH)
0x53aa
(16 bits)
D15–8
–
reserved – – – 0 when being read.
D7–0
TC[23:16]
Time base counter high-order
8-bit data
0x0–0xff 0x0 R/W
D[7:0]/RFC_TCH, D[15:0]/RFC_TCL
TC[23:0]: Time Base Counter Bits
Time base counter data can be read and written to. (Default: 0x0)
Note: The time base counter must be set from the low-order value (TC[15:0]/RFC_TCL register) first.
The counter may not be set to the correct value if the high-order value (TC[23:16]/RFC_TCH reg-
ister) is written first.
RFC Interrupt Mask Register (RFC_IMSK)
Register name Address Bit Name Function Setting Init. R/W Remarks
RFC Interrupt
Mask
Register
(RFC_IMSK)
0x53ac
(16 bits)
D15–5
–
reserved – – – 0 when being read.
D4
OVTCIE
TC overflow error interrupt enable 1 Enable 0 Disable 0 R/W
D3
OVMCIE
MC overflow error interrupt enable 1 Enable 0 Disable 0 R/W
D2
ESENBIE
Sensor B oscillation completion
interrupt enable
1 Enable 0 Disable 0 R/W
D1
ESENAIE
Sensor A oscillation completion
interrupt enable
1 Enable 0 Disable 0 R/W
D0
EREFIE
Reference oscillation completion
interrupt enable
1 Enable 0 Disable 0 R/W
D[15:5] Reserved
D4 OVTCIE: TC Overflow Error Interrupt Enable Bit
Enables or disables time
base counter overflow error interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D3 OVMCIE: MC Overflow Error Interrupt Enable Bit
Enables or disables measurement counter overflow error interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D2 ESENBIE: Sensor B Oscillation Completion Interrupt Enable Bit
Enables or disables sensor B oscillation completion interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D1 ESENAIE: Sensor A Oscillation Completion Interrupt Enable Bit
Enables or disables sensor A o
scillation completion interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D0 EREFIE: Reference Oscillation Completion Interrupt Enable Bit
Enables or disables reference oscillation completion interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)