Epson S1C17624 - Contents

CONTENTS
S1C17624/604/622/602/621 TECHNICAL MANUAL
Seiko Epson Corporation
i
– Contents –
1 Overview ........................................................................................................................1-1
1.1 Features ...........................................................................................................................1-1
1.2 Block Diagram ..................................................................................................................1-3
1.3 Pins/Pads .........................................................................................................................1-4
1.3.1 S1C17624 Pin Configuration Diagram ...............................................................1-4
1.3.2 S1C17604 Pin Configuration Diagram ...............................................................1-7
1.3.3 S1C17622 Pin
Configuration Diagram ..............................................................1-10
1.3.4 S1C17602/621 Pin Configuration Diagram .......................................................1-13
1.3.5 Pin Descriptions ................................................................................................1-17
2 CPU ................................................................................................................................2-1
2.1 Features of the S1C17 Core ............................................................................................2-1
2.2 CPU Registers .................................................................................................................2-2
2.3 Instruction Set ..................................................................................................................2-2
2.4 Reading PSR ...................................................................................................................2-5
2.5 Processor Information ......................................................................................................2-6
3 Memory Map..................................................................................................................3-1
3.1 Bus Cycle .........................................................................................................................3-3
3.1.1 Restrictions on Access Size...............................................................................3-3
3.1.2 Restrictions on Instruction Execution Cycles ........................................
.............3-3
3.2 Flash Area ........................................................................................................................3-4
3.2.1 Embedded Flash Memory ..................................................................................3-4
3.2.2 Flash Programming ...........................................................................................3-4
3.2.3 Prot
ect Bits ........................................................................................................3-4
3.2.4 Access Control for the Flash Controller ............................................................3-5
FLASHC Control Register (MISC_FL) ....................................................................................... 3-5
3.3 Internal RAM Area............................................................................................................3-6
3.3.1 Embedded RAM ................................................................................................3-6
IRAM Size Select Register (MISC_IRAMSZ) ............................................................................ 3-6
3.4 Display RAM Area ............................................................................................................3-7
3.5 Internal Peripheral Area ...................................................................................................3-7
3.5.1 Internal Peripheral Area 1 (0x4000–) .................................................................3-7
3.5.2 Internal Peripheral Area 2 (0x5000–) .........................................................
........3-8
3.6 S1C17 Core I/O Area .......................................................................................................3-8
4 Power Supply ................................................................................................................4-1
4.1 Power Supply Voltage (VDD) .............................................................................................4-1
4.2 Analog Power Supply Voltage (AVDD) ...............................................................................4-1
4.3 Internal Power Supply Circuit ...........................................................................................4-1
4.4 Controlling the Power Supply Circuit ................................................................................4-2
4.5 Heavy Load Protection Function ......................................................................................4-3
4.6 Control Register Details ...................................................................................................4-3
VD1 Control Register (VD1_CTL) ............................................................................................... 4-3
LCD Voltage Regulator Control Register (LCD_VREG) ............................................................ 4-4
5 Initial Reset ...................................................................................................................5-1
5.1 Initial Reset Sources ........................................................................................................5-1
5.1.1 #RESET Pin .....................................
..................................................................5-1
5.1.2 P0 Port Key-Entry Reset ...................................................................................5-1
5.1.3 Resetting by the Watchdog Timer ......................................................................5-2
5.2 Initial Reset Sequence .........................................................................
............................5-2