Epson S1C17624 - Page 5

CONTENTS
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Seiko Epson Corporation
S1C17624/604/622/602/621 TECHNICAL MANUAL
5.3 Initial Settings After an Initial Reset ................................................................................5-2
6 Interrupt Controller (ITC) .............................................................................................6-1
6.1 ITC Module Overview .......................................................................................................6-1
6.2 Vector Table ......................................................................................................................6-2
Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH) .............................. 6-3
6.3 Control of Maskable Interrupts .........................................................................................6-4
6.3.1 Interrupt Control Bits in Peripheral Modul
es ......................................................6-4
6.3.2 ITC Interrupt Request Processing .....................................................................6-4
6.3.3 Interrupt Processing by the S1C17 Core ...........................................................6-5
6.4 NMI ...............................................................................................................
....................6-6
6.5 Software Interrupts ...........................................................................................................6-6
6.6 HALT and SLEEP Mode Cancellation ..............................................................................6-6
6.7 Control Register Details ...................................................................................................6-6
Interrupt Level Setup Register x (ITC_LVx) ............................................................................... 6-7
7 Clock Generator (CLG) .................................................................................................7-1
7.1 CLG Module Overview .....................................................................................................7-1
7.2 CLG Input/Output Pins .....................................................................................................7-2
7.3 Oscillators ........................................................................................................................7-2
7.3.1 IOSC Oscillator ..................................................................................................7-2
7.3.2 OSC3 Oscil
lator .................................................................................................7-3
7.3.3 OSC1 Oscillator .................................................................................................7-4
7.4 System Clock Switching ...................................................................................................7-6
7.5 CPU Core Clock (CCLK) Control ......
...............................................................................7-7
7.6 Peripheral Module Clock (PCLK) Control .........................................................................7-7
7.7 Clock External Output (FOUTH, FOUT1) .........................................................................7-9
7.8 RESET and NMI Input Noise Filters ................................................................................7-10
7.9 Control Register Details ..................................................................................................7-10
Prescaler Control Register (PSC_CTL) .................................................................................... 7-10
Clock Source Select Register (OSC_SRC) .............................................................................. 7-10
Oscillation Control Register (OSC_CTL) .................................................................................. 7-11
Noise Filter Enable Register (OSC_NFEN) .............................................................................. 7-13
FOUT Control Register (OSC_FOUT) ...................................................................................... 7-13
PCLK Control Register (CLG_PCLK) ....................................................................................... 7-14
CCLK Control Register (CLG_CCLK)....................................................................................... 7-15
8 Real-Time Clock (RTC) .................................................................................................8-1
8.1 RTC Module Overview .....................................................................................................8-1
8.2 RTC Counters ..................................................................................................................8-2
8.3 RTC Control .....................................................................................................................8-4
8.3.1 Operating Clock Control .....
................................................................................8-4
8.3.2 RTC Initial Sequence .........................................................................................8-4
8.3.3 12/24-hour Mode and Counter Settings .............................................................8-5
8.3.4 Start/Stop and Software Reset ....................................................
......................8-5
8.3.5 Counter Hold and Busy Flag ..............................................................................8-6
8.3.6 30-second Correction ........................................................................................8-6
8.3.7 Counter Read ....................................................................................................8-7
8.4 RTC Interrupt
s ..................................................................................................................8-8
8.5 Details of Control Registers .............................................................................................8-9
RTC Clock Control Register (RTC_CC) .................................................................................... 8-9
RTC Interrupt Status Register (RTC_INTSTAT) ....................................................................... 8-10
RTC Interrupt Mode Register (RTC_INTMODE) ...................................................................... 8-10
RTC Control 0 Register (RTC_CNTL0) .................................................................................... 8-11