Epson S1C17624 - I2 C Slave Interrupt Control Register (I2 CS_ICTL)

21 I
2
C SLAVE (I2CS)
21-16
Seiko Epson Corporation S1C17624/604/622/602/621 TECHNICAL MANUAL
D0 R/W: Read/Write Direction Bit
Represents the transfer direction bit value.
1 (R): Output (master read operation)
0 (R): Input (master write operation) (default)
The transfer direction bit value that has been received with the slave address is set to R/W. Use R/W to
select the transmit- or receive-handling.
I
2
C Slave Interrupt Control Register (I2CS_ICTL)
Register name Address Bit Name Function Setting Init. R/W Remarks
I
2
C Slave
Interrupt Control
Register
(I2CS_ICTL)
0x436c
(16 bits)
D15–3
–
reserved – – – 0 when being read.
D2
BSTAT_IEN
Bus status interrupt enable 1 Enable 0 Disable 0 R/W
D1
RXRDY_IEN
Receive interrupt enable 1 Enable 0 Disable 0 R/W
D0
TXEMP_IEN
Transmit interrupt enable 1 Enable 0 Disable 0 R/W
D[15:3] Reserved
D2 BSTAT_IEN: Bus Status Interrupt Enable Bit
Enables or disables the bus status interrupt.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When BSTAT_IEN is set to 1, I
2
C bus status interrupt requests to the ITC are enabled. A bus status in-
terrupt req
uest occurs when BSTAT/I2CS_STAT register is set to 1. (See description of BSTAT.)
When BSTAT_IEN is set to 0, a bus status interrupt will not be generated.
D1 RXRDY_IEN: Receive Interrupt Enable Bit
Enables or disables the I2CS receive interrupt.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When RXRDY_IEN is set to 1, I2CS receive interrupt requests to the ITC are enabled. A receive inter-
rupt request occurs when the data received in the
shift register is loaded to the I2CS_RECV register
(receive operation completed). When RXRDY_IEN is set to 0, a receive interrupt will not be generated.
D0 TXEMP_IEN: Transmit Interrupt Enable Bit
Enables or disables the I2CS transmit interrupt.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When TXEMP_IEN is set to 1, I2CS transmit interrupt requests to the ITC are enabled. A transmit in-
terrupt request occurs when the data written to the
I2CS_TRNS register is transferred to the shift regis-
ter. When TXEMP_IEN is set to 0, a transmit interrupt will not be generated.