2 CPU
S1C17624/604/622/602/621 TECHNICAL MANUAL
Seiko Epson Corporation
2-1
CPU2
The S1C17624/604/622/602/621 contains the S1C17 Core as its core processor.
The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor.
It features low power consumption, high-speed operation, large address space, main instructions executable in one
clock cycle, and a small sized design. The S1C17 Core is suitable for embedded applications such as controllers
and sequencers for which
an eight-bit CPU is commonly used.
For details of the S1C17 Core, refer to the “S1C17 Family S1C17 Core Manual.”
Features of the S1C17 Core2.1
Processor type
• Seiko Epson original 16-bit RISC processor
• 0.35–0.15 µm low power CMOS process technology
Instruction set
• Code length: 16-bit fixed length
• Number of instructions: 111 basic instructions (184 including variations)
• Execution cycle: Main ins
tructions executed in one cycle
• Extended immediate instructions: Immediate extended up to 24 bits
• Compact and fast instruction set optimized for development in C language
Register set
• Eight 24-bit general-purpose registers
• Two 24-bit special registers
• One 8-bit special register
Memory space and bus
• Up to 16M bytes of memory space (24-bit address)
• Harvard architecture using separated instructi
on bus (16 bits) and data bus (32 bits)
Interrupts
• Reset, NMI, and 32 external interrupts supported
• Address misaligned interrupt
• Debug interrupt
• Direct branching from vector table to interrupt handler routine
• Programmable software interrupts with a vector number specified (all vector numbers specifiable)
Power saving
• HALT (halt instruction)
• SLEEP (slp instruction)
Coprocessor interface
• 16-bit × 16
-bit multiplier
• 16-bit ÷ 16-bit divider
• 16-bit × 16-bit + 32-bit multiply and accumulation unit
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