Epson S1C17624 - T16 A Comparator;Capture Ch.x A Data Registers (T16 A_CCAx); T16 A Comparator;Capture Ch.x B Data Registers (T16 A_CCBx); T16 A Comparator;Capture Ch.x Interrupt Enable Registers (T16 A_IENx)

13 16-BIT PWM TIMERS (T16A2)
13-18
Seiko Epson Corporation S1C17624/604/622/602/621 TECHNICAL MANUAL
T16A Comparator/Capture Ch.x A Data Registers (T16A_CCAx)
Register name Address Bit Name Function Setting Init. R/W Remarks
T16A
Comparator/
Capture Ch.x A
Data Register
(T16A_CCAx)
0x5406
0x5426
(16 bits)
D15–0
CCA[15:0]
Compare/capture A data
CCA15 = MSB
CCA0 = LSB
0x0 to 0xffff 0x0 R/W
D[15:0] CCA[15:0]: Compare/Capture A Data Bits
In comparator mode (CCAMD/ T16A_CCCTLx register = 0)
Sets a compare A data, which will be compared with the counter value, through this register.
The counter value comparison timing varies according to the CBUFEN/T16A_CTLx register value. For
more information, see “Comparator mode (CCAMD/CCBMD = 0, default)”
in Section 13.4.1.
Note: After the T16A_CCAx register has been set, wait for one or more T16A2 count clock cycles
and then run the counter.
In capture mode (CCAMD = 1)
When the counter value is captured at the external trigger signal (CAPAx) edge selected using
CAPATRG[1:0]/T16A_CCCTLx register, the captured value is loaded to this register. At the same time
a capture A interrupt can be generated, thus the captured counter value can be read out in the interrupt
handler.
T16A Comparator/Capture Ch.x B Data Registers (T16A_CCBx)
Register name Address Bit Name Function Setting Init. R/W Remarks
T16A
Comparator/
Capture Ch.x B
Data Register
(T16A_CCBx)
0x5408
0x5428
(16 bits)
D15–0
CCB[15:0]
Compare/capture B data
CCB15 = MSB
CCB0 = LSB
0x0 to 0xffff 0x0 R/W
D[15:0] CCB[15:0]: Compare/Capture B Data Bits
In comparator mode (CCBMD/ T16A_CCCTLx register = 0)
Sets a compare B data, which will be compared with the counter value, through this register.
The counter value comparison timing varies according to the CBUFEN/T16A_CTLx register value. For
more information, see “Comparator mode (CCAMD/CCBMD = 0, default)”
in Section 13.4.1.
Note: After the T16A_CCBx register has been set, wait for one or more T16A2 count clock cycles
and then run the counter.
In capture mode (CCBMD = 1)
When the counter value is captured at the external trigger signal (CAPBx) edge selected using CAPB-
TRG[1:0]/T16A_CCCTLx register, the captured value is loaded to this register. At the same time a
capture B interrupt can be generated, thus the captured counter value can be read out in the interrupt
handler.
T16A Comparator/Capture Ch.x Interrupt Enable Registers (T16A_IENx)
Register name Address Bit Name Function Setting Init. R/W Remarks
T16A
Comparator/
Capture Ch.x
Interrupt Enable
Register
(T16A_IENx)
0x540a
0x542a
(16 bits)
D15–6
–
reserved – – – 0 when being read.
D5
CAPBOWIE
Capture B overwrite interrupt enable 1 Enable 0 Disable 0 R/W
D4
CAPAOWIE
Capture A overwrite interrupt enable 1 Enable 0 Disable 0 R/W
D3
CAPBIE
Capture B interrupt enable 1 Enable 0 Disable 0 R/W
D2
CAPAIE
Capture A interrupt enable 1 Enable 0 Disable 0 R/W
D1
CBIE
Compare B interrupt enable 1 Enable 0 Disable 0 R/W
D0
CAIE
Compare A interrupt enable 1 Enable 0 Disable 0 R/W
D[15:6] Reserved