1 OVERVIEW
S1C17624/604/622/602/621 TECHNICAL MANUAL
Seiko Epson Corporation
1-11
Chip (S1C17622)
Y
X
(0, 0)
4.256 mm
4.200 mm
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
AV
DD
V
SS
P15(EXCL3)/AIN5
P14(EXCL2)/AIN6
P13(EXCL1)/AIN7
P12/SIN0
P11/SOUT0
P10/SCLK0
P07/#SPISS0
P06/SDI0
P05/SDO0
P04/SPICLK0
P52/SIN1
P51/SOUT1
P50/SCLK1
P47/TOUT4
P46/RFCLKO
P45/SDA1
P44/SCL1
P03/#ADTRG
P02(EXCL0)
P01/REMI
P00/REMO
#RESET
TEST
OSC1
OSC2
V
D1
V
SS
OSC3
OSC4
V
DD
VSS
V
C1
VC2
VC3
CA
CB
N.C.
N.C.
N.C.
COM0
COM1
COM2
COM3
SEG55/COM4
SEG54/COM5
SEG53/COM6
SEG52/COM7
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SCLK1/AIN4/P16
AIN3/P17
AIN2/P20
AIN1/P21
AIN0/P22
V
DD
SENB0/P23
SENA0/P24
REF0/P25
RFIN0/P26
V
SS
SOUT1/RFIN1/P27
SIN1/REF1/P30
SCL0/SENA1/P31
SDA0/SENB1/P32
#BFR/P53
LFRO/P54
P55
P56
SCL1/SCL0/P33
SDA1/SDA0/P34
FOUT1/#BFR/P35
TOUT3/RFCLKO/P36
TOUTN3/LFRO/TOUT4/P37
FOUTH/P40
P41/DSIO
P42/DST2
P43/DCLK
N.C.
SEG0
SEG1
SEG2
SEG3
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Die No.
CJ624D***
3.3.2 S1C17622 Pad Configuration DiagramFigure 1.
Chip size X = 4.200 mm, Y = 4.256 mm
Pad opening No. 1 to 32, 66 to 97: X = 87 µm, Y = 85 µm
No. 33 to 65, 98 to 130: X = 85 µm, Y = 87 µm
Chip thickness 400 µm
* The S1C17622 chip has the same pad configuration and coordinates as those of the S1C17624.
However, 16-bit PWM timer (T16A2) input/output signals (EXCL5, TOUTA5/CAPA5, TOUTB5/CAPB5,
EXCL6, T
OUTA6/CAPA6, and TOUTB6/CAPB6) are not assigned to the S1C17622 pads.
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