Epson S1C17624 - Page 9

CONTENTS
vi
Seiko Epson Corporation
S1C17624/604/622/602/621 TECHNICAL MANUAL
16.6 SWT Interrupts ..............................................................................................................16-3
16.7 Control Register Details ................................................................................................16-4
Stopwatch Timer Control Register (SWT_CTL) ........................................................................ 16-4
Stopwatch Timer BCD Counter Register (SWT_BCNT) ........................................................... 16-4
Stopwatch Timer Interrupt Mask Register (SWT_IMSK) .......................................................... 16-5
Stopwatch Timer Interrupt Flag Register (SWT_IFLG)............................................................. 16-5
17 Watchdog Timer (WDT) ..............................................................................................17-1
17.1 WDT Module Overview .................................................................................................17-1
17.2 Operation Clock.............................................................................................................17-1
17.3 WDT Control ..................................................................................................................17-1
17.3.1 NMI/Reset Mode Selection .............................................................................17-1
17.3.2 WDT Run/Stop Control ...................................................................................17-1
17.3.3 WDT Reset .....................................................................................................17-2
17.
3.4 Operations in HALT and SLEEP Modes .........................................................17-2
17.4 Control Register Details ................................................................................................17-2
Watchdog Timer Control Register (WDT_CTL) ........................................................................ 17-2
Watchdog Timer Status Register (WDT_ST) ............................................................................ 17-3
18 UART ...........................................................................................................................18-1
18.1 UART Module Overview ................................................................................................18-1
18.2 UART Input/Output Pins ................................................................................................18-2
18.3 Transfer Clock ................................................................................................................18-2
18.4 Transfer Data Settings ...................................................................................................18-2
18.5 Data Transfer Control ....................................................................................................18-3
18.6 Receive Errors...............................................................................................................18-5
18.7 UART Interrupts ............................................................................................................18-6
18.8 IrDA Interface ................................................................................................................18-7
18.9 Control Register Details ................................................................................................18-8
UART Ch.x Status Registers (UART_STx) ............................................................................... 18-8
UART Ch.x Transmit Data Registers (UART_TXDx)................................................................ 18-10
UART Ch.x Receive Data Registers (UART_RXDx) ................................................................ 18-10
UART Ch.x Mode Registers (UART_MODx) ........................................................................... 18-10
UART Ch.x Control Registers (UART_CTLx) .......................................................................... 18-11
UART Ch.x Expansion Registers (UART_EXPx) ..................................................................... 18-12
19 SPI ...............................................................................................................................19-1
19.1 SPI Module Overview ....................................................................................................19-1
19.2 SPI Input/Output Pins ....................................................................................................19-1
19.3 SPI Clock ......................................................................................................................19-2
19.4 Data Transfer Condition Settings ...................................................................................19-2
19.5 Data Transfer Control ....................................................................................................19-3
19.6 SPI Interrupts ................................................................................................................19-5
19.7 Control Register Details ................................................................................................19-6
SPI Ch.x Status Register (SPI_STx) ........................................................................................ 19-6
SPI Ch.x Transmit Data Register (SPI_TXDx) .......................................................................... 19-7
SPI Ch.x Receive Data Register (SPI_RXDx) .......................................................................... 19-7
SPI Ch.x Control Register (SPI_CTLx)..................................................................................... 19-7
20 I
2
C Master (I2CM) .......................................................................................................20-1
20.1 I2CM Module Overview .................................................................................................20-1
20.2 I2CM Input/Output Pins .................................................................................................20-1
20.3 Synchronization Clock ...................................................................................................20-2
20.4 Settings Before Data Transfer .......................................................................................20-2