B 4235 / H41q-MS (0605)
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2 Modules
2.1 Central module F 8652X
The central module for safety related applications with TÃœV certificate of the PES H41q-MS
contains the essential functions demonstrated in the block diagram of the central module:
Figure 2: Block diagram of the central module F 8652X
– two clock-synchronized microprocessors
– each microprocessor with an own memory, one processor operates with real data and pro-
gram and the other one with inverted data and program
– testable hardware comparer for all the external accesses of both microprocessors, in case
of a fault the watchdog will be set to the safe status and the status of the processor is
announced
– Flash-EPROMs of the program memory for the operating system and the user program
usable for min. 100,000 writing cycles
– Data memory in sRAM
– Multiplexer to connect I/O bus, DPR and redundant CU (not used in the H41q-MS system)
– Battery backup of the sRAMs via batteries with monitoring
– 2 interfaces RS 485 with galvanic isolation. Transmission rate: max. 57600 bps
– 4digit diagnostic display and 2 LEDs for information out of the system, I/O level and user
program
– Dual Port RAM for fast memory access to the second central module (not used in the
H41q-MS system)
Note Operating system/resource type in ELOP II
The assembly kit is usable since operating system BS41q/51q V7.0-8.
Resource type in ELOP II: H41qce-MS.
Watchdog
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