Model 5340A
Theory of Operation
pulse is determined by
R20 and C19. The multivibrator can be retriggered
at
any time during the
50 psec period to establish
a
new 50 psec pulse output.
As long
as
the multivibrator is retrig-
gered within 50 psec, the Q output U3(10)
will
remain high. In practice, this
is
the manner in
which the circuit operates. Since U2 turns on and off for each cycle of
its
input, U3B will be
retriggered as long
as
the signal
at
UZ(2)
is
sufficient to trigger comparator U2. When lock is
achieved, U3B(10)
is
high.
4
-
166. In the phase detector portion of A8, C16 couples the
20
kHz mixer signal through a high
impedance tie point to Q2. The high impedance tie point prevents humidity from discharging
the high impedance points and
C18. Q2
is
an N
-
channel insulated gate field
-
effect transistor
(IGFET) used
as
a sampler, U3A generates 0.8 psec
(*0.2
psec) pulses to gate Q2 on and off at
the
20
kHz reference rate. The mixer signal from All
is
sampled by QZ to produce
a
charge
across C18. When the mixer signal is
at
20
kHz and is coherent with the
20
kHz reference signal,
the voltage across
c18 will be dc. When the loop
is
out of lock, the voltage across C18
is
ac. The
frequency
of
this ac is the difference between the instantaneous values of the reference signal
and the mixer signal. U3A is disabled when
U3B(10)
is
low, thereby preventing sampler
operation until the transfer loop SEARCH line goes high.
This prevents false locks on har
-
monics of
20
kHz such
as
10 kHz, 40 kHz, etc.
4
-
167. Q1A and Q1B comprise
a
dc stabilized FET pair. Connecting Q1A and Q1B between
+
and
-
15 volts reduces the dc variation on the output of pin
6.
CR2 and CR3 provide
*lo
volts for
proper operation of
Q1A and Q1B. C20 through C23 filter out noise generated in the Zener diodes.
4
-
168. When phase lock
is
achieved, the dc output of Q1A and Q1B
is
amplified by DC Com
-
pensator/Amplifier
No.
2
A9. A9 drives the VCO
2
(A10) frequency to maintain
a
20 kHz differ
-
ence frequency out of All which
is
phase coherent with the 20 kHz reference signal.
4
-
169.
A9 DC
AMPLlFIER/COMPENSATOR NO.
2
ASSEMBLY, 05340
-
60007
4
-
170.
This assembly (Figure 8
-
15) performs two main functions. One of the functions provides
dc amplification and compensation required for the loop gain and frequency response charac
-
teristics. The other function is to process the search and lock signals to develop
a
transfer loop
lock output to “tell” the counter circuits when the transfer loop
is
locked.
I
4
-
171.
U1
is
a
low
-
noise operational amplifier which provides dc gain combined with
a
lag net
-
work. The dc gain
is
variable from approximately
1
to 25
as
determined by the ratio of R8 to
R4
+
R2.
R1 inserts a current into the operational amplifier input to adjust the dc offset. The lag
network consists of C5, C7,
R11, and R8. At higher frequencies,
C5
and C7 increase the amount
of feedback to reduce the gain.
Figure 4
-
50 shows the frequency response
of
amplifier U1. The
rolloff characteristics are designed to provide the proper compensation for the loop.
Figure 4
-
50. Frequency Response of A9 Input Amplifier
GAIN
,
,
I!
’1
:.I
i
FREQ
4
-
40
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