HP 5340A Service Manual

Model 5340A
Theory of Operation
4 - 243. For example, assume we are completing the step in the fifth symbol in Figure 5 - 4 marked
“Done
? 14”. ROM U3 input on pins 14, 13, 12, 11, and 10 is LLHLH and will output LLHLHHLL
on pins
9, 7, 6, 5, 4, 3, 2, and 1, respectively. For the present program address, U4’s output will be
HLHH HHHL on pins
1, 2, 3, 4, 5, 6, 7, and 9, respectively.
4 - 244. U13 will select action #11, (“Start Delay”) by activating U5D, U5C, U9B.
U12 will select
test
#14 (“Done?”) that will drive U12(10) low when the delay is complete. U2’s input on pins
11, 6, 13, 4, and 3 will be LLHLL, respectively, as U1 switches to the Oc OB and OA inputs,
because of the low from
U12. At the next clock pulse, U2 will feed the LLHLL on its input to U3
and U4.
4
- 245. U3 will then output LHHH HHLH.
U4 will output HLLH HLLL, causing U13 to select
action
#9 (clear) and causing U12 to select test #8 (“Direct?”).
4 - 246. If U12 does not sense a DIRect signal, UlZ(l0) will output a H, causing U2 to be fed a
LHHHH for the next address. If
a DIRect signal is sensed, U1 will select the other three lines of
U3, causing U2 to be fed LH HLH for the next address. Note that in the first case, the next action
would have been
#6 (INH) and in the second case the next action would have been #1 (R. Count).
Thus we control the paths through the flow chart.
-
4 - 247. A22 HIGH FREQUENCY COUNTER ASSEMBLY, 05340 - 60016
4 - 248. This assembly (Figure 8 - 29) contains the first two decade counters of the decade counting
chain. Logic switch
U8 selects either the direct count or the HI Z input and provides an output
which is shaped by Schmitt trigger
U9. Data switch U3B selects between the VCO input and the
check signal.
Data switch
U3A selects the input for main gate/decade counter U2B. U6 is the
main gate flip
- flop, which is controlled by differential amplifier Q4 and QlO. Q4-QlO converts
the
TI’L signal from A20 to the EECL logic levels required by U6. The + 10 output of U2A feeds
7 2 circuit U7, which drives U4 after passing through EECL to TTL level shifter circuitry Q17-Q20.
4 - 249.
The outputs of U2 and U7 are EECL (0 to -0.6V). Q13 through Q16 convert this to ECL
(0.85 to -1.5V).
U1 shifts the ECL to TTL (approximately +2.5V to OV). U5 receives the four line
output from each decade counter and multiplexes the information (transfers it one line
at a time)
to
A23 after counting has been completed. The logic revels on U5 (pins 3 and 13) determine which
line is outputted.
4 - 250. The output of U7 is EECL and connects to emitter follower Q17 which in turn feeds
differential amplifier
Q18-Q20. The differential amplifier drives saturated switch Q19 giving
TTL levels at the collector of Q19. This is fed to +5 circuit U4 and also outputed via U5. CR1 is a
catcher diode to keep
Q19 from complete saturation. Differential amplifiers Ql-Q7, Q2-Q8, etc.,
shift
from TTL control levels to the EECL needed for the IC’s.
The RC network (C3, R4, etc.)
speeds up the transition time.
4 - 251. A23 COUNT REGISTER ASSEMBLY, 05340 - 60030
4 - 252.
When the m(paralle1 entry) line at
A23, pin K is high, U7 receives inputs from A23, pin 13 via U18A, U15B, and U14C. This input is
derived from
A22U4. U7 through U2 are a series of decade counters and shift registers with U2 1
being the most significant digit. When the main gate on A22 is open U7, U6, U5, U4, U3, and U2
will count the output of A22U4. This counter chain will contain the 102 to 107 digits of the meas -
urement. PE goes high when the main gate on A22 closes. The output of the two least significant
digits on
A22 must then be shifted 1 - bit at a time into A23U8 and U9 through A22U5. U16A
and B generate the 00, 01, 11, and 10 code necessary to shift the BCD data for the 100 and 101
digits into U8 and U9. , ,
4 - 253. By pulling PE low,, tpe control board A21 initiates shifting of the BCD data in A23U2
through A23U9 into A24. ,Ih the direct count mode, the information is fed in directly. In the
phase lock mode, it is qecessary to subtract
20 MHz from the stored information because of the
20 MHz IF circuit.
Flexibility
is obtained by being able to add or subtract. UlO, U11, U21, U18,
U19B, and U20 comprise a BCD adder/subtractor. A BCD “2” is generated on A19 and routed
Refer to Figure
8 - 30 for the schematic diagram.
4 - 49

HP 5340A Specifications

General

Brand	HP
Model	5340A
Category	Cash Counter
Language	English