HP 5340A - Low-Power BCD Decade Counter 1820-0669; Five-Bit Comparator 1820-0706; Low-Power Quad Two-Input Multiplexer 1820-0710

Model 5340A
Theory of Operation
4 - 61. Low - Power BCD Decade Counter 1820 - 0669
4 - 62.
Figure 4 - 28 shows the logic diagram and pin connections for the 1820 - 0669. The counter
is fully synchronous with the clock pulse driving four master/slave flip - flops in parallel through
a clock buffer. During the low to high clock transition, the master is inhibited from further
change. After the masters are locked out, data
is transferred from the master to the slaves and
reflected
at the outputs. When the clock is high, the masters are inhibited and the master/slave
data path remains established. During the high to low transition of the clock, the slave is in -
hibited from further change, followed by the enabling of the masters forthe acceptance of data
from the counting logic or the parallel entry logic. The control inputs, PE, CEP, and CET, select
the operating mode
as shown in the tables below. During the count mode, the rising edge of the
clock changes the counters to the next state of count sequence shown in the state diagram below.
4 - 63. men PE is low, the unit can be synchronously preset from the four parallel inputs PO - P3.
When PE and the clock are low, each master of the flip - flops is connected to the appropriate
parallel input and the slaves are steady in their previous state. When the clock goes high, the
masters are inhibited and the information
is tranferred to the slaves and reflected at the outputs.
The parallel enable input overrides both count enable inputs, presetting the counter when low.
4 - 64. Terminal count is high when the counter is at terminal count (state 9), and CET is high.
Without using additional logic, multistage synchronous counting
at high speeds is possible with
a high speed look
- ahead technique. The asynchronous master reset (active low) overrides all
other inputs to reset the four outputs low.
4 - 65. Five - Bit Comparator 1820 - 0706
4 - 66. This IC (Figure 4 - 29) is a high - speed expandable comparator which compares two 5 - bit
words
to give one of three outputs: “equal to”, “less than”, or “greater than”. An active low
enable line
is provided to enable the comparator function. When the enable line is high, all three
outputs are held low. For words containing more than
&bits, comparators can be connected in
series by respectively connecting the A>B and A<B outputs of the first comparator to the A0 and
BO inputs of the next comparator. The truth table shows the logic operation.
4 - 67. Low - Power Quad Two - Input Multiplexer 1820 - 0710
4 - 68. The multiplexer consists of four multiplexing circuits with common select and enable logic.
Each circuit contains two inputs and one output. The logic symbol and truth table are shown
in Figure
4 - 30.
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