Omron CP1L - Page 740

706
PLC Setup Appendix G
2 2-3 2-3-6 Received
Bytes
256 bytes 256 bytes Every cycle 165
(CP1L M-
type CPU
Unit)
00 to
07
00 hex
1 byte 01 hex
: :
255 bytes FF hex
2-3-7 Set End
Code
0x0000 0x0000 Every cycle 164
(CP1L M-
type CPU
Unit)
00 to
07
00 hex
: :
0x00FF FF hex
2-3-8 Delay 0: 0 × 10 ms 0: 0 × 10 ms Every cycle 162
(CP1L M-
type CPU
Unit)
00 to
15
0000 hex
: :
9999: 9999 × 10 ms 270F hex
2-4 ToolBus (peripheral bus)
2-4-1 Baud 9,600 bps 9,600 bps Every cycle 161
(CP1L M-
type CPU
Unit)
00 to
07
00 or
06 hex
19,200 bps 07 hex
38,400 bps 08 hex
57,600 bps 09 hex
115,200 bps 0A hex
2-5 Serial Gateway
2-5-1 Baud 9,600 bps 300 bps Every cycle 161
(CP1L M-
type CPU
Unit)
00 to
07
01 hex
600 bps 02 hex
1,200 bps 03 hex
2,400 bps 04 hex
4,800 bps 05 hex
9,600 bps 00 or
06 hex
19,200 bps 07 hex
38,400 bps 08 hex
57,600 bps 09 hex
115,200 bps 0A hex
2-5-2 Format
(data
length,
stop bits,
parity)
7,2,E: 7-bit
data, 2 stop
bits, even parity
7,2,E: 7-bit data, 2 stop
bits, even parity
Every cycle 160
(CP1L M-
type CPU
Unit)
00 to
03
0 hex
7,2,O: 7-bit data, 2 stop
bits, odd parity
1 hex
7,2,N: 7-bit data, 2 stop
bits, no parity
2 hex
7,1,E: 7-bit data, 2 stop
bits, even parity
4 hex
7,1,O: 7-bit data, 1 stop
bit, odd parity
5 hex
7,1,N: 7-bit data, 1 stop
bit, no parity
6 hex
8,2,E: 8-bit data, 2 stop
bits, even parity
8 hex
8,2,O: 8-bit data, 2 stop
bits, odd parity
9 hex
8,2,N: 8-bit data, 2 stop
bits, no parity
A hex
8,1,E: 8-bit data, 1 stop
bit, even parity
C hex
8,1,O: 8-bit data, 1 stop
bit, odd parity
D hex
8,1,N: 8-bit data, 1 stop
bit, no parity
E hex
2-5-3 Response
Timeout
50:
50 × 100 ms =
5 s
50: 50 × 100 ms = 5 s Every cycle 167
(CP1L M-
type CPU
Unit)
08 to
15
00 hex
1: 1 × 100 ms 01 hex
: :
255: 255 × 100 ms FF hex
Name Default Settings When setting is read
by CPU Unit
Internal
address
Bits Settings