10.3 High-speed Counter Instruction
10.3.1 [F0 MV] High-speed Counter Control Instruction
Performs the controls such as the software reset, disabling the count and clearing the high-
speed counter instruction.
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Instruction format
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Operand
Operand Settings
S Area storing the control code of the high-speed counter or constant data
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Memory area type that can be specified
Operand WX WY WR WL SV EV DT LD I
Constant
Index
modifier
K H
S ● ● ● ● ● ● ● ● ● ● ● ●
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Outline of operation
● Performs the high-speed counter control according to the control code specified by [S].
● This instruction is used when performing the following operations with the high-speed
counter.
1. When performing the software reset
2. When disabling the count
3. When disabling the reset input by an external input temporarily
4. When canceling the control executed by the high-speed counter instruction F165
(CAM0) / F166 (HC1S) / F167 (HC1R) or when clearing the target value match interrupt
● The control codes once written are held until the next writing.
● The control code written by the F0 (MV) instruction is written to the special data register
DT90052. At the same time, it is written to the control code monitor area. The written data is
the data for lower 8 bits only.
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Precautions during programming
● The setting of disabling the rest input is valid only when allocating the reset input in the
system register.
● In the external reset input setting for the transistor output type, the reset input (X6 or X7)
allocated to the Control Unit input is switched between enable and disable. In the reset input
setting for the relay output type, the pulse I/O cassette reset input (X102 or X202) allocated
10.3 High-speed Counter Instruction
WUME-FPXHPOSG-01 10-11
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