Point Grey Flea3 FL3-U3 - Video Mode Control and Status Registers

Point Grey Flea3 USB 3.0 Technical Reference Appendix A: Control and Status Registers
Offset Name Field Bit Description
260h
:
2BFh
Reserved
2E0h V_CSR_INQ_7_0 Mode_0 [0-31] CSR 32-bit offset for Format 7 Mode 0
2E4h V_CSR_INQ_7_1 Mode_1 [0-31] CSR 32-bit offset for Format 7 Mode 1
2E8h V_CSR_INQ_7_2 Mode_2 [0-31] CSR 32-bit offset for Format 7 Mode 2
2ECh V_CSR_INQ_7_3 Mode_3 [0-31] CSR 32-bit offset for Format 7 Mode 3
2F0h V_CSR_INQ_7_4 Mode_4 [0-31] CSR 32-bit offset for Format 7 Mode 4
2F4h V_CSR_INQ_7_5 Mode_5 [0-31] CSR 32-bit offset for Format 7 Mode 5
2F8h V_CSR_INQ_7_6 Mode_6 [0-31] CSR 32-bit offset for Format 7 Mode 6
2FCh V_CSR_INQ_7_7 Mode_7 [0-31] CSR 32-bit offset for Format 7 Mode 7
300h V_CSR_INQ_7_8 Mode_8 [0-31] CSR 32-bit offset for Format 7 Mode 8
304h V_CSR_INQ_7_9 Mode_9 [0-31] CSR 32-bit offset for Format 7 Mode 9
308h V_CSR_INQ_7_10 Mode_10 [0-31] CSR 32-bit offset for Format 7 Mode 10
30Ch V_CSR_INQ_7_11 Mode_11 [0-31] CSR 32-bit offset for Format 7 Mode 11
310h V_CSR_INQ_7_12 Mode_12 [0-31] CSR 32-bit offset for Format 7 Mode 12
314h V_CSR_INQ_7_13 Mode_13 [0-31] CSR 32-bit offset for Format 7 Mode 13
318h V_CSR_INQ_7_14 Mode_14 [0-31] CSR 32-bit offset for Format 7 Mode 14
31Ch V_CSR_INQ_7_15 Mode_15 [0-31] CSR 32-bit offset for Format 7 Mode 15
320h V_CSR_INQ_7_16 Mode_16 [0-31] CSR 32-bit offset for Format 7 Mode 16
324h V_CSR_INQ_7_17 Mode_17 [0-31] CSR 32-bit offset for Format 7 Mode 17
328h V_CSR_INQ_7_18 Mode_18 [0-31] CSR 32-bit offset for Format 7 Mode 18
32Ch V_CSR_INQ_7_19 Mode_19 [0-31] CSR 32-bit offset for Format 7 Mode 19
330h V_CSR_INQ_7_20 Mode_20 [0-31] CSR 32-bit offset for Format 7 Mode 20
334h V_CSR_INQ_7_21 Mode_21 [0-31] CSR 32-bit offset for Format 7 Mode 21
338h V_CSR_INQ_7_22 Mode_22 [0-31] CSR 32-bit offset for Format 7 Mode 22
33Ch V_CSR_INQ_7_23 Mode_23 [0-31] CSR 32-bit offset for Format 7 Mode 23
340h V_CSR_INQ_7_24 Mode_24 [0-31] CSR 32-bit offset for Format 7 Mode 24
344h V_CSR_INQ_7_25 Mode_25 [0-31] CSR 32-bit offset for Format 7 Mode 25
348h V_CSR_INQ_7_26 Mode_26 [0-31] CSR 32-bit offset for Format 7 Mode 26
34Ch V_CSR_INQ_7_27 Mode_27 [0-31] CSR 32-bit offset for Format 7 Mode 27
350h V_CSR_INQ_7_28 Mode_28 [0-31] CSR 32-bit offset for Format 7 Mode 28
354h V_CSR_INQ_7_29 Mode_29 [0-31] CSR 32-bit offset for Format 7 Mode 29
358h V_CSR_INQ_7_30 Mode_30 [0-31] CSR 32-bit offset for Format 7 Mode 30
35Ch V_CSR_INQ_7_31 Mode_31 [0-31] CSR 32-bit offset for Format 7 Mode 31
A.3 Video Mode Control and Status Registers
These registers provide partial image size format (Format 7, Mode x) information.
Revised 9/27/2012
Copyright ©2011-2012 Point Grey Research Inc.
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