14. Serial I/O
puorG92/C61M
page 201
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 14.23 Transfer to U2RB Register and Interrupt Timing
(4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1
(3) When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0
SDA2
SCL2
Receive interrupt
(DMA request)
Transmit interrupt
SDA2
SCL2
The above timing applies to the following setting :
• The CKDIR bit in the U2MR register is set to 1 (slave)
(1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (No clock delay)
D
6
D
5
D
4
D
3
D
2
D
1
D
8
(ACK or NACK)D
7
SDA2
SCL2
D
0
ACK interrupt (DMA
request) or NACK interrupt
(2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay)
SDA2
SCL2
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
b15
•••
b9 b8 b7 b0
D
8
Contents of the U2RB register
b15
•••
b9 b8 b7 b0
b15
•••
b9 b8 b7 b0
b15
•••
b9 b8 b7 b0 b15
•••
b9 b8 b7 b0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
6
D
5
D
4
D
3
D
2
D
1
D
7
D
0
ACK interrupt (DMA
request) or NACK interrupt
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
6
D
5
D
4
D
3
D
2
D
1
D
7
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
6
D
5
D
4
D
3
D
2
D
1
D
7
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
(ACK or NACK)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
D
8
(ACK or NACK)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
D
8
(ACK or NACK)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Receive interrupt
(DMA request)
Transmit interrupt
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Contents of the U2RB register
Contents in the U2RB register
Contents in the U2RB register
Contents in the U2RB register
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