16. MULTI-MASTER I
2
C bus INTERFACE
puorG92/C61M
page 261
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 16.6 S3D0 Register
0: S
CL
output logic value = 0
1: S
CL
output logic value = 1
0: S
DA
output logic value = 0
1: S
DA
output logic value = 1
0: S
CL
I/O pin
1: Port output pin
0: S
DA
I/O pin
1: Port output pin
0: Disable the I
2
C bus interface
interrupt of data receive
completion
1: Enable the I
2
C bus interface
interrupt of data receive
completion
When setting NACK
(ACK bit = 0), write 0
0: Disable the I
2
C bus interface
interrupt of STOP condition
detection
1: Enable the I
2
C bus interface
interrupt of STOP condition
detection
I C bus system clock
selection bits,
if bits ICK4 to ICK2 in the
S4D0 register is 000
2
2
The logic value monitor
bit of S
CL
output
The logic value monitor
bit of S
DA
output
S
CL
/port function switch
bit
(1)
S
DA
/port function switch
bit
(1)
The interrupt enable bit for
data receive completion
The interrupt enable bit for
STOP condition detection
ICK1
ICK0
SCLM
SDAM
PEC
PED
WIT
SIM
FunctionBit NameBit Symbol
00110000
2
After Reset
02E6
16
AddressSymbol
S3D0
0
ontrol Re
ister 1
2
7
4
2b1b0
RW
b7 b6
0 0 :
0 1 :
1 0 :
V
IIC
=1/2 f
IIC
=1/4f
IIC
=1/8 f
IIC
1 1 :
Reserved
V
IIC
V
IIC
RW
RW
RW
RW
RO
RO
RW
RW
NOTE:
1. Bits PED and PEC are enabled when the ES0 bit in the S1D0 register is set to 1 (I
2
C bus interface enabled).
2. When the PCLK0 bit in the PCLKR register is set to 0, f
IIC
=f
2
. When the PCLK0 bit in the PCLKR register is set
to 1, f
IIC
=f
1
.
(2)
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