Renesas M16C/29 Series - Page 31

1. Overview
page 5
puorG92/C61M
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 1.2 is a block diagram of the M16C/29 Group, 64-pin package.
Figure 1.2 M16C/29 Group, 64-Pin Block Diagram
O u t p u t ( T i m e r A ) : 5
I n p u t ( T i m e r B ) : 3
I n t e r n a l P e r i p h e r a l F u n c t i o n s
W a t c h d o g t i m e r
( 1 5 b i t s )
D M A C
( 2 c h a n n e l s )
Memory
ROM
(1)
R A M
( 2 )
U A R T / C l o c k s y n c h r o n o u s S I / O
( 8 b i t s x 3 c h a n n e l s )
System clock generator
X
I N- XO U T
XC I N- XC O U T
O n - c h i p o s c i l l a t o r
P L L f r e q u e n c y s y n t h e s i z e r
M 1 6 C / 6 0 S e r i e s C P U C o r e
R0L
R0H
R1H
R1L
R2
R3
A0
A1
FB
SB
ISP
U S P
INTB
Multiplier
8
P
o
r
t
P
1
0
4
P
o
r
t
P
9
8
P
o
r
t
P
8
P
o
r
t
P
7
8
P
o
r
t
P
6
8
Port P2
8
P C
FLG
T i m e r ( 1 6 b i t s )
3 - p h a s e P W M
P o r t P 3
4
Port P1
3
I / O P o r t s
Port P0
4
T i m e r S
I n p u t c a p t u r e /
O u t p u t c o m p a r e
T i m e m e a s u r e m e n t : 8 c h a n n e l s
W a v e f o r m g e n e r a t i n g : 8 c h a n n e l s
C l o c k s y n c h r o n o u s S I / O
( 8 b i t s x 1 c h a n n e l )
M u l t i - m a s t e r I
2
C b u s
(
)
A / D c o n v e r t e r
( 1 0 b i t s x 1 6 c h a n n e l s )
CRC calculation circuit
(CRC-CCITT, CRC16)
CAN module
(1 channel)
NOTES:
1. The ROM capacity varies depending on each product.
2. The RAM capacity varies depending on each product.