Renesas M16C/29 Series - Page 311

16. MULTI-MASTER I
2
C bus INTERFACE
puorG92/C61M
page 285
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Figure 16.21 The bit reset timing (The STOP condition detection)
Figure 16.22 The bit reset timing (The START condition detection)
MST
TRX
BB flag
S
DA
S CL
Bit reset signal
Related bits
1.5 V IIC cycle
BB flag
S
DA
SCL
Bit reset signal
BC2 - BC0
TRX (in slave mode)
Related bits
Figure 16.23 Bit set/reset timing ( at the completion of data transfer)
S CL
Bit set signal
AAA
1V IIC c
y
cle
PIN bit
AA
2V IIC cycle
Bit reset signal
AAAAA
AAAAA
BC0 - BC2
MST(When in arbitration lost)
TRX(When in NACK receive in slave
transmit mode)
The bits referring
to reset
AAAAA
AAAAA
TRX(ALS=0 meanwhile the slave
receive R/W bit = 1
The bits referring
to set