Test Procedure SME
1038.6002.02 5.36 E-13
Bit no.: 081 082 083 084 085 086 087 088 089 090
Contents:0001000100
Bit no.: 091 092 093 094 095 096 097 098 099 100
Contents:1011111010
Bit no.: 101 102 103 104 105 106 107 108 109 110
Contents:0100110001
Bit no.: 111 112 113 114 115 116 117 118 119 120
Contents:0100001001
Bit no.: 121 122 123 124 125 126 127 128 129 130
Contents:0011011010
Bit no.: 131 132 133 134 135 136 137 138 139 140
Contents:1000111010
Bit no.: 141 142 143 144 145 146 147 148 149 150
Contents:1100101101
Bit no.: 151 152 153 154 155 156 157 158 158 160
Contents:0000001111
Bit no.: 161 ... 1250
Contents: 111...
À For LEV ATT, enter the following bit pattern:
Bit 1 to 8 must be "1".
Bit 9 to 159 must be "0".
Bit 160 to 1250 must be "1".
À Settings at the FSE
- PRESET
- CENTER 890.2 MHz
- REF 20 dBm
- MODE VECTORANALYZER
- MARKER SEARCH SUM MKR ON
RMS phase error) .............................................. <1° (0.7° typically).
Peak phase error................................................ <3° (2.7° typically).
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