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Tektronix 7613 User Manual

Tektronix 7613
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Circuit
Description—7613/R7613
Service
C59
cannot
change
its
charge
instantaneously,
the
sudden
change
in
voltage
at
the
emitter
of
Q1
pulls
the
emitter
of
Q2
positive
also,
to
reverse-bias
it.
With
Q2
reverse
biased,
its
collector
rises
positive
to
produce
a
positive
output
level
at
pin
14
(see
time
T,
on
the
waveforms).
Now,
conditions
are
reversed.
Since
Q2
is
reverse
biased,
there
is
no
current
through
it.
Therefore,
C59
can
begin
to
discharge
through
R59.
The
emitter
level
of
Q2
follows
the
discharge
of
C59
until
it
reaches
a
level
about
0.6
volt
more
negative
than
its
base.
Then
Q2
is
forward
biased
and
its
collector
drops
negative
to
reverse-bias
Q1.
The
level
at
pin
14
drops
negative
also,
to
complete
the
cycle.
Once
again,
C59
begins
to
charge
through
R56-R57
to
start
the
second
cycle.
Two
outputs
are
provided
from
this
oscillator.
The
Delay
Ramp
signal
from
the
junction
of
R56-R57
is
connected
to
the
Vertical
Chopped
Blanking
stage.
This
signal
has
the
same
waveshape
as
shown
by
the
waveform
at
pin
13,
with
its
slope
determined
by
the
divider
ratio
between
R56-R57.
A
square-wave
output
is
provided
at
pin
14.
The
frequency
of
this
square
wave
is
determined
by
the
RC
relationship
between
C59
and R1.
The
duty
cycle
is
determined
by
the
ratio
of
R56-R57
to
R59.
The
square
wave
at
pin
14
is
connected
to
pin
16
through
C60. C60,
along
with
the
internal
resistance
of
US5A,
differentiates
the
square
wave
at
pin
14
to
produce
a
negative-going
pulse
coincident
with
the
falling
edge
of
the
square
wave
(positive-going
pulse
coincident
with
rising
edge
has
no
effect
on
circuit
operation).
This
negative-going
pulse
is
connected
to
pin
15
through
an
inverter-shaper
which
is
also
part
of
U55A.
The
output
at
pin
15
is
a
positive-going
Clock
pulse
at
a
repetition
rate
of
about
two
megahertz.
Vertical
Chopped
Blanking
The
Vertical
Chopped
Blanking
stage
is
made
up
of
the
remaining
half
of
integrated
circuit
U55B,
Fig.
3-6A.
This
stage
determines
if
Vertical
Chopped
Blanking
pulses
are
re-
quired,
based
upon
the
operating
mode
of
the
vertical
system
or
the
plug-in
units
(dual
trace
units
only).
Vertical
Chopped
Blanking
pulses
are
produced
if:
(1)
VERT
MODE
switch
is
set to
CHOP:
(2)
dual-trace
vertical
unit
is
operating
in
the
chopped
mode
and
that
unit
is
being
displayed;
(3)
dual-trace
vertical unit
is
operating
in
the
chopped
mode
with
the
VERT
MODE
switch
set to
ADD.
The
repetition
rate
of
the
negative-going
Vertical
Chopped
Blanking
pulse
output
at
pin
4
is
always
two
megahertz
as
determined
by
the
Clock
Generator
stage.
The
Delay
Ramp
signal
from
the
Clock
Generator
stage
determines
the
repetition
rate
and
pulse
width
of
the
Vertical
Chopped
Blanking
pulses.
The
Delay
Ramp
applied
to
pin 10
starts
to
go
negative
from
a
level
of
about
+1.1
volts
coincident
with
the
leading
edge
of
the
Clock
pulse
(see
waveforms
in
Fig.
3-5B).
This
results
in
a
HI
quiescent
condition
for
the
Vertical
Chopped
Blanking
pulse.
The
slope
of
the
negative-going
Delay
Ramp
is
determined
by
the
Clock
Generator
stage.
As
it
reaches
a
level
slightly
negative
from
ground,
the
Vertical
Chopped
Blanking
pulse
output
level
changes
to
the
LO
state.
This
signal
remains
LO
until
the
Delay
Ramp
goes
HI
again.
Notice
the
delay
between
the
leading
edge
of
the
Clock
pulse
generated
by
U55A
and
the
leading
edge
of
the
Vertical
Chopped
Blanking
pulses
(see Fig.
3-5B).
The
amount
of
delay
between
the
leading
edges
of
these
pulses
is
determined
by
the
slope
of
the
Delay
Ramp
applied
to
pin
10.
This
delay
is
necessary
due
to
the
delay
line
in
the
vertical
deflection
system.
Otherwise,
the
trace
blanking
resulting
from
the
Vertical
Chopped
Blanking
pulse
would
not
coincide
with
the
switching
between
the
displayed
traces.
The
duty
cycle
of
the
square
wave
produced
in
the
Clock
Generator
stage
determines
the
pulse
width
of
the
Vertical
Chopped
Blanking
pulses
(see
Clock
Generator
discussion
for
more
information).
To
|
CHOP
Mode
(vert)
—~»-)
3
Clock,
Pin
|
|
US5B
15
U55B
|
Left
Plug-In
Mode
og
i
(Chop
Inhibit)
| |
Vertical
Mode
=
jG
Verticat
!
|
Command
4
|=
Chopped
pay
|
Blanking
Pin
10
|
ADD
Meade
(vert)
>»)
7
USSB
|
Right
Plug-In
Mode
:
(Chop
Inhibit)
8
ora
|
Delay
Ramp
40
Blanking
|
|
Pina
|
ussB
|
{|
(A)
(B)
Delay
Fig.
3-5.
(A)
Input
and
output
pins
for
Vertical
Chopped
Blanking
stage,
(B)
Idealized
waveforms
for
Vertical
Chopped
Blanking
stage.
3-10
REV.
MAY
1974
7613

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Tektronix 7613 Specifications

General IconGeneral
BrandTektronix
Model7613
CategoryTest Equipment
LanguageEnglish

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