Xilinx Virtex-5 RocketIO GTP User Manual

38 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 1: Introduction to the RocketIO GTP Transceiver
R
TX_XCLK_SEL_0
TX_XCLK_SEL_1
Selects the clock used to drive the clock
domain in the PCS following the TX buffer.
Set to TXOUT (TXOUTCLK) when using
the TX buffer. Set to TXUSR (TXUSRCLK)
when bypassing the TX buffer.
TX Buffering, Phase Alignment,
and Buffer Bypass (page 105)
TXRX_INVERT0
TXRX_INVERT1
Controls inverters that optimize the clock
paths within the GTP transceiver. When
bypassing the TX buffer, set to 00100.
Otherwise, set to 00000.
TX Buffering, Phase Alignment,
and Buffer Bypass (page 105)
Table 1-4: GTP_DUAL Attribute Summary (Continued)
Attribute Description Section (Page)

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English