Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 47
UG196 (v1.3) May 25, 2007
Examples
R
The period of the PLL can be calculated using Equation 3-2 and Equation 3-3.
Equation 3-2
Equation 3-3
The terms used in Equation 3-2 and Equation 3-3 are defined as follows:
• REFCLK is the speed of the clock tied to the CLKIN input of the GTP_DUAL tile in
MHz.
• PLL_DIVSEL_REF is an attribute that defines the dividing factor of the reference clock
divider of the shared PLL.
• PLL_DIVSEL_FB is an attribute that defines the dividing factor of the feedback
divider (which acts like a multiplication factor) of the shared PLL.
• DIV = 5 when INTDATAWIDTH = 1 (10-bit mode)
• DIV = 4 when INTDATAWIDTH = 0 (8-bit mode)
PCI Express Example
To calculate PLL SPEED and SIM_PLL_PERDIV2 for the PCI Express example, the
following values are assigned:
• REFCLK = 100 MHz
• PLL_DIVSEL_REF = 2
• DIV = 5
• PLL_DIVSEL_FB = 5
Using Equation 3-2, PLL SPEED is 1.25 GHz, meaning that the period is 800 ps. Using
Equation 3-3, SIM_PLL_PERDIV2 is 800 divided by 2 equal to 400 decimal or 190
hexadecimal.
Gigabit Ethernet Example
To calculate PLL SPEED and SIM_PLL_PERDIV2 for the Gigabit Ethernet example, the
following values are assigned:
• REFCLK = 125 MHz
• PLL_DIVSEL_REF = 1
• DIV = 5
• PLL_DIVSEL_FB = 2
Using Equation 3-2, PLL SPEED is 1.25 GHz, meaning that the period is 800 ps. Using
Equation 3-3, SIM_PLL_PERDIV2 is 800 divided by 2 or 400 decimal (190 hexadecimal).
XAUI Example
To calculate PLL SPEED and SIM_PLL_PERDIV2 for the XAUI example, the following
values are assigned:
• REFCLK = 156.25 MHz
• PLL_DIVSEL_REF = 1
• DIV = 5
• PLL_DIVSEL_FB = 2
PLL SPEED
REFCLK
PLL_DIV_REF
---------------------------------------
⎝⎠
⎛⎞
DIV× PLL_DIVSEL_FB()×=
SIM_PLL_PERDIV2
1 PLL SPEED⁄()
2
-------------------------------------------=

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English