ABB REB650 - Page 157

IA
|DI|
a
b
a>b
DIPU
One cycle
delay
VA
a
b
a>b
One cycle
delay
DVPU
|DV|
a
b
a>b
AND
DVDI detection Phase 1
VPPU
DVDI detection Phase 2
Same logic as for phase 1
IB
VB
DVDI detection Phase 3
Same logic as for phase 1
IC
VC
a
b
a<b
VA
IA
a
b
a>b
50P
AND
AND
52A
OR
OR
AND
a
b
a<b
VB
IB
a
b
a>b
AND
AND
OR
OR
AND
a
b
a<b
VC
IC
a
b
a>b
AND
AND
OR
OR
AND
OR
FuseFailDetDVDI
DVDI Detection
ANSI10000034-2-en.vsd
0
20 ms
0
1.5 cycle
ANSI10000034 V2 EN
Figure 59: Simplified logic diagram for DV/DI detection part
1MRK 505 277-UUS C Section 9
Secondary system supervision
151
Technical Manual