Abov MC96F8204 Series

112
MC96F8204
ABOV Semiconductor Co., Ltd.
TnCRL (Timer n Control Low Register) : 98H/B0H, Where n = 1 and 2
7
6
5
4
3
2
1
0
TnCK2
TnCK1
TnCK0
TnIFR
RLDnEN
TnPOL
TnECE
TnCNTR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
TnCK[2:0]
Select Timer n clock source. fx is main system clock frequency
TnCK2
TnCK1
TnCK0
Description
0
0
0
fx/2048
0
0
1
fx/512
0
1
0
fx/64
0
1
1
fx/8
1
0
0
fx/4
1
0
1
fx/2
1
1
0
fx/1
1
1
1
External clock (ECn)
TnIFR
When Tn Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or
auto clear by INT_ACK signal. Writing “1” has no effect.
0
Tn Interrupt no generation
1
Tn Interrupt generation
RLDnEN
Control Timer n Reload Signal
0
Enable timer n reload signal
1
Disable timer n reload signal
TnPOL
TnO/PWMnO Polarity Selection
0
Start High (TnO/PWMnO is low level at disable)
1
Start Low (TnO/PWMnO is high level at disable)
TnECE
Timer n External Clock Edge Selection
0
External clock falling edge
1
External clock rising edge
TnCNTR
Timer n Counter Read Control
0
No effect
1
Load the counter value to the B data register (When write, automatically
cleared “0” after being loaded)