Abov MC96F8204 Series

122
MC96F8204
ABOV Semiconductor Co., Ltd.
11.8.2 UART Block Diagram
RXD
Rx
Control
Clock
Recovery
Receive Shift Register
(RXSR)
Data
Recovery
DOR/PE/FE
Checker
USTDR[0], USTRX8[0], (Rx)
USTDR[1], USTRX8[1], (Rx)
TXD
Tx
Control
Stop bit
Generator
Parity
Generator
Transmit Shift Register
(TXSR)
USTDR, USTTX8, (Tx)
USTP[1:0]
M
U
X
LOOPS
TXC
TXCIE DRIE
DRE
Empty signal
To interrupt
block
INT_ACK
Clear
RXC
RXCIEWAKEIE
WAKE
At Stop mode
To interrupt
block
SCLK
(fx: System clock)
Low level
detector
2
USTS[2:0]
3
USTS[2:0]
3
TXE
RXE
DBLS
USTSB
Baud Rate Generator
USTBD
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
SCK
ACK
Control
Clock
Sync Logic
Master
USTMS[1:0]
M
U
X
M
U
X
USTMS[1:0]
USTMS[1:0]
2
2
2
Figure 11.25 UART Block Diagram