Abov MC96F8204 Series

75
MC96F8204
ABOV Semiconductor Co., Ltd.
10.8 Interrupt Enable Accept Timing
Figure 10.7 Interrupt Response Timing Diagram
10.9 Interrupt Service Routine Address
Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISR
10.10 Saving/Restore General-Purpose Registers
Figure 10.9 Saving/Restore Process Diagram and Sample Source
Main Task
Saving
Register
Restoring
Register
Interrupt
Service Task
INTxx : PUSH PSW
PUSH DPL
PUSH DPH
PUSH B
PUSH ACC
∙
∙
Interrupt_Processing:
∙
∙
POP ACC
POP B
POP DPH
POP DPL
POP PSW
RETI
02H
25H
00B3H
00B4H
Basic Interval Timer
Vector Table Address
0EH
2EH
0125H
0126H
Basic Interval Timer
Service Routine Address
01H
00B5H
Interrupt
Latched
Interrupt
goes
Active
System
Clock
Max. 4 Machine Cycle
4 Machine Cycle
Interrupt Processing
: LCALL & LJMP
Interrupt Routine