Abov MC96F8204 Series User Manual

77
MC96F8204
ABOV Semiconductor Co., Ltd.
10.12 Interrupt Register Overview
10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3)
Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24
peripherals are able to control interrupt.
10.12.2 Interrupt Priority Register (IP, IP1)
The 24 interrupts are divided into 6 groups which have each 4 interrupt sources. A group can be assigned 4 levels
interrupt priority using interrupt priority register. Level 3 is the highest priority, while level 0 is the lowest priority. After a
reset IP and IP1 are cleared to ‘00H’. If interrupts have the same priority level, lower number interrupt is served first.
10.12.3 External Interrupt Flag Register (EIFLAG)
The external interrupt flag (EIFLAG) is set to ‘1’ when the external interrupt generating condition is satisfied. The flag is
cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing ‘0’ to it.
10.12.4 External Interrupt Polarity Register (EIPOL0, EIPOL1)
The external interrupt polarity 0 register (EIPOL0) and external interrupt polarity 1 register (EIPOL1) determines which
type of rising/falling/both edge interrupt. Initially, default value is no interrupt at any edge.
10.12.5 Register Map
Name
Address
Direction
Default
Description
IE
A8H
R/W
00H
Interrupt Enable Register
IE1
A9H
R/W
00H
Interrupt Enable Register 1
IE2
AAH
R/W
00H
Interrupt Enable Register 2
IE3
ABH
R/W
00H
Interrupt Enable Register 3
IP
B8H
R/W
00H
Interrupt Priority Register
IP1
F8H
R/W
00H
Interrupt Priority Register 1
EIFLAG
C0H
R/W
00H
External Interrupt Flag Register
EIPOL0
A4H
R/W
00H
External Interrupt Polarity 0 Register
EIPOL1
A5H
R/W
00H
External Interrupt Polarity 1 Register
Table 10.3 Interrupt Register Map

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English