Abov MC96F8204 Series User Manual

70
MC96F8204
ABOV Semiconductor Co., Ltd.
10.3 Block Diagram
0
0
0
0
Priority High
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
Priority Low
EA
Release
Stop/Sleep
Reserved
Timer 0
Timer 1
Timer 2
IP1IP
IE2
T0IFR
T1IFR
Reserved
USART Rx
USART Tx
Level 0
Level 1
Level 2
Level 3
IE1
Reserved
ADC
Reserved
WT
WDT
BIT
IE3
ADCIFR
WDTIFR
BITIFR
Reserved
IE0
Reserved
Reserved
EINT10
EIFLAG.2
FLAG10
EIPOL1
EINT11
EIFLAG.3
FLAG11
EINT12
EIFLAG.4
FLAG12
EINT0
EIFLAG.0
FLAG0
EIPOL0
EINT1
EIFLAG.1
FLAG1
EIPOL0
Reserved
T2IFR
Reserved
I2C
I2CIFR
Figure 10.2 Block Diagram of Interrupt
NOTE)
1. The release signal for stop/idle mode may be generated by all interrupt sources which are enabled
without reference to the priority level.
2. An interrupt request is delayed while data are written to IE, IE1, IE2, IE3, IP, IP1, and PCON register.

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English