Abov MC96F8204 Series User Manual

152
MC96F8204
ABOV Semiconductor Co., Ltd.
11.9.11 Register Description for I2C
I2CDR (I2C Data Register) : ECH
7
6
5
4
3
2
1
0
I2CDR7
I2CDR6
I2CDR5
I2CDR4
I2CDR3
I2CDR2
I2CDR1
I2CDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
I2CDR[7:0]
The I2CDR transmit buffer and receive buffer share the same I/O address with this
DATA register. The transmit data buffer is the destination for data written to the
I2CDR register. Reading the I2CDR register returns the contents of the receive
buffer.
I2CSDHR (I2C SDA Hold Time Register) : EDH
7
6
5
4
3
2
1
0
I2CSDHR7
I2CSDHR6
I2CSDHR5
I2CSDHR4
I2CSDHR3
I2CSDHR2
I2CSDHR1
I2CSDHR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 01H
I2CSDHR[7:0]
The register is used to control SDA output timing from the falling edge of SCL.
Note that SDA is changed after t
SCLK
X (I2CSDHR+2), in master mode, load half the
value of I2CSCLR to this register to make SDA change in the middle of SCL.
In slave mode, configure this register regarding the frequency of SCL from master.
The SDA is changed after tsclk X (I2CSDHR+2) in master mode. So, to insure
operation in slave mode, the value
t
SCLK
X (I2CSDHR +2) must be smaller than the period of SCL.
I2CSCHR (I2C SCL High Period Register) : EFH
7
6
5
4
3
2
1
0
I2CSCHR7
I2CSCHR6
I2CSCHR5
I2CSCHR4
I2CSCHR3
I2CSCHR2
I2CSCHR1
I2CSCHR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 3FH
I2CSCHR[7:0]
This register defines the high period of SCL in master mode.
The base clock is SCLK, the system clock, and the period is calculated by the
formula: t
SCLK
X (4 X I2CSCHR + 2) where
t
SCLK
is the period of SCLK.
So, the operating frequency of I2C master mode is calculated by the following equation.
I2CSCLR (I2C SCL Low Period Register) : EEH
7
6
5
4
3
2
1
0
I2CSCLR7
I2CSCLR6
I2CSCLR5
I2CSCLR4
I2CSCLR3
I2CSCLR2
I2CSCLR1
I2CSCLR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 3FH
I2CSCLR[7:0]
This register defines the low period of SCL in master mode.
The base clock is SCLK, the system clock, and the period is calculated by the
formula: t
SCLK
X (4 X I2CSCLR + 2) where
t
SCLK
is the period of SCLK.
f
I2C
=
t
SCLK
X (4 X (I2CSCLR + I2CSCHR) + 4)
1

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English