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ABOV Semiconductor Co., Ltd.
11.8.4 External Clock (SCK)
External clocking is used in the synchronous or SPI slave mode of operation.
External clock input from the SCK pin is sampled by a synchronization logic to remove meta-stability. The output from
the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.
This process introduces two CPU clock period delay. The maximum frequency of the external SCK pin is limited up-to
1MHz.
11.8.5 Synchronous mode operation
When synchronous or SPI mode is used, the SCK pin will be used as either clock input (slave) or clock output
(master). Data sampling and transmitter is issued on the different edge of SCK clock each other. For example, if data
input on RXD (MISO in SPI mode) pin is sampled on the rising edge of SCK clock, data output on TXD (MOSI in SPI
mode) pin is altered on the falling edge.
The CPOL bit in USTCR1 register selects which SCK clock edge is used for data sampling and which is used for data
change. As shown in the figure below, when CPOL is zero, the data will be changed at rising SCK edge and sampled
at falling SCK edge.
Figure 11.27 Synchronous Mode SCK Timing
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