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ABOV Semiconductor Co., Ltd.
11.8.10 SPI Mode
The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features.
− Full Duplex, Three-wire synchronous data transfer
− Mater and Slave Operation
− Supports all four SPIn modes of operation (mode 0, 1, 2, and 3)
− Selectable LSB first or MSB first data transfer
− Double buffered transmit and receive
− Programmable transmit bit rate
When SPI mode is enabled (USTMS[1:0]=”11”), the slave select (SS) pin becomes active LOW input in slave mode
operation, or can be output in master mode operation if USTSSEN bit is set to ‘0’.
Note that during SPI mode of operation, the pin RXD is renamed as MISO and TXD is renamed as MOSI for
compatibility to other SPI devices.
11.8.11 SPI Clock Formats and Timing
To accommodate a wide variety if synchronous serial peripherals from different manufacturers, the USART has a clock
polarity bit (CPOL) and a clock phase control bit (CPHA) to select one of four clock formats for data transfers. CPOL
selectively insert an inverter in series with the clock. CPHA chooses between two different clock phase relationships
between the clock and data. Note that CPHA and CPOL bits in USTCR1 register have different meanings according to
the USTMS[1:0] bits which decides the operating mode of USART.
Table below shows four combinations of CPOL and CPHA for SPI mode 0, 1, 2, and 3.
Table 11.11 CPOL Functionality
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