Abov MC96F8204 Series

134
MC96F8204
ABOV Semiconductor Co., Ltd.
11.8.12 USART SPI Block Diagram
RXCIE
Rx Control
Receive Shift Register
(RXSR)
Data
Recovery
DOR Checker USTDR[0], (Rx)
Tx Control
Transmit Shift Register
(TXSR)
USTDR, (Tx)
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
M
U
X
LOOPS
TXC
TXCIE DRIE
DRE
Empty signal
To interrupt
block
INT_ACK
Clear
RXC
Baud Rate Generator
USTBD
TXE
SCLK
(fx: System clock)
MISO
MOSI
M
U
X
MASTER
D
E
P
FXCH
SCK
SCK
Control
MASTER
RXE
To interrupt
block
M
U
X
Edge Detector
And
Controller
SS
SS
Control
CPHACPOL
ORD
(MSB/LSB-1st)
USTDR[1], (Rx)
USTSSEN
NOTE)
1. The P06 should be configured as “I/O Port” by P0FSRH[1:0] bits on SPI slave mode of USART..
Figure 11.34 USART SPI Block Diagram