Abov MC96F8204 Series

29
MC96F8204
ABOV Semiconductor Co., Ltd.
7.12 UART Characteristics
(T
A
=-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f
XIN
=11.1MHz)
Parameter
Symbol
MIN
TYP
MAX
Unit
Serial port clock cycle time
t
SCK
1250
t
CPU
x 16
1650
ns
Output data setup to clock rising edge
t
S1
590
t
CPU
x 13
–
Clock rising edge to input data valid
t
S2
–
–
590
Output data hold after clock rising edge
t
H1
t
CPU
- 50
t
CPU
–
Input data hold after clock rising edge
t
H2
0
–
–
Serial port clock High, Low level width
t
HIGH
, t
LOW
470
t
CPU
x 8
970
Table 7.12 UART Characteristics
t
HIGH
t
LOW
t
SCK
Figure 7.3 Waveform for UART Timing Characteristics
Shift Clock
Data Out D1 D2 D3 D4 D5 D6 D7D0
ValidData In Valid Valid Valid Valid Valid Valid Valid
tSCK
tS1
tH1
tH2
tS2
Figure 7.4 Timing Waveform for the UART Module