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ABOV Semiconductor Co., Ltd.
10.6 Effective Timing after Controlling Interrupt Bit
Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3)
Figure 10.4 Effective Timing of Interrupt Enable Register
Case b) Interrupt flag Register
Figure 10.5 Effective Timing of Interrupt Flag Register
Interrupt Flag Register
Command
After executing next instruction,
interrupt flag result is effective.
Interrupt Enable Register
command
After executing IE set/clear, enable
register is effective.
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