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ABOV Semiconductor Co., Ltd.
11.8.3 USART Clock Generation
Figure 11.26 Clock Generation Block Diagram (USART)
The clock generation logic generates the base clock for the transmitter and receiver. The USART supports four modes
of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave
synchronous mode. The clock generation scheme for master SPI and slave SPI mode is the same as master
synchronous and slave synchronous operation mode. The USTMS[1:0] bits in USTCR1 register selects asynchronous
or synchronous operation. Asynchronous double speed mode is controlled by the DBLS bit in the USTCR2 register.
The MASTER bit in USTCR3 register controls whether the clock source is internal (master mode, output pin) or
external (slave mode, input pin). The SCK pin is active only when the USART operates in synchronous or SPI mode.
Following table shows the equations for calculating the baud rate (in bps).
Equation for Calculating Baud Rate
Asynchronous Normal Mode (DBLS=0)
Baud Rate =
fx
16(USTBD + 1)
Asynchronous Double Speed Mode (DBLS=1)
Baud Rate =
fx
8(USTBD + 1)
Synchronous or SPI Master Mode
Baud Rate =
fx
2(USTBD + 1)
Table 11.10 Equations for Calculating USART Baud Rate Register Setting
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