Abov MC96F8204 Series

116
MC96F8204
ABOV Semiconductor Co., Ltd.
Figure 11.24 A/D Converter Operation Flow
SET ADCCRH
SET ADCCRL
AFLAG = 1?
Converting START
READ ADCDRH/L
ADC END
Select ADC Clock and Data Align Bit.
ADC enable & Select AN Input Channel.
Start ADC Conversion.
If Conversion is completed, AFLAG is set “1” and ADC interrupt is
occurred.
After Conversion is completed, read ADCDRH and ADCDRL.
Y
N