Abov MC96F8204 Series

119
MC96F8204
ABOV Semiconductor Co., Ltd.
ADCCRH (A/D Converter Control High Register) : A1H
7
6
5
4
3
2
1
0
ADCIFR
–
–
–
TRIG
ALIGN
CKSEL1
CKSEL0
R/W
–
–
–
R/W
R/W
R/W
R/W
Initial value : 00H
ADCIFR
When ADC Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or
auto clear by INT_ACK signal.
0
ADC Interrupt no generation
1
ADC Interrupt generation
TRIG
A/D Trigger Signal Selection(The ADC module is automatically disabled at stop mode)
0
ADST
1
Timer 1 A match signal
ALIGN
A/D Converter data align selection.
0
MSB align (ADCDRH[7:0], ADCDRL[7:4])
1
LSB align (ADCDRH[3:0], ADCDRL[7:0])
CKSEL[1:0]
A/D Converter Clock selection
CKSEL1
CKSEL0
Description
0
0
fx/1
0
1
fx/2
1
0
fx/4
1
1
fx/8