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Abov MC96F8204 Series User Manual

Abov MC96F8204 Series
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148
MC96F8204
ABOV Semiconductor Co., Ltd.
I2C can choose one of the following cases according to the RXACK flag in I2CSR.
1) Master continues receiving data from slave. To do this, set ACKEN bit in I2CCR to Acknowledge the next
data to be received.
2) Master wants to terminate data transfer when it receives next data by not generating ACK signal. This can
be done by clearing ACKEN bit in I2CCR.
3) Because no ACK signal is detected, master terminates data transfer. In this case, set the STOPC bit in
I2CCR.
4) No ACK signal is detected, and master transmits repeated START condition. In this case, load SLA+R/W
into the I2CDR and set the STARTC bit in I2CCR.
After doing one of the actions above, clear to 0b” all interrupt source bits in I2CSR to release SCL line. In
case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In case of 4), move
to step 6 after transmitting the data in I2CDR, and if transfer direction bit is 0 go to master transmitter
section.
9. This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that
data transfer between master and slave is over. To clear I2CSR, write 0 value to I2CSR. After this, I2C
enters idle state.

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Abov MC96F8204 Series Specifications

General IconGeneral
BrandAbov
ModelMC96F8204 Series
CategoryMicrocontrollers
LanguageEnglish

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