Abov MC96F8204 Series User Manual

164
MC96F8204
ABOV Semiconductor Co., Ltd.
FCDIN (Flash CRC Data IN Register): D7H
7
6
5
4
3
2
1
0
FCDIN7
FCDIN6
FCDIN5
FCDIN4
FCDIN3
FCDIN2
FCDIN1
FCDIN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
FCDIN[7:0]
Flash CRC Data In
NOTE)
1. Used only to Auto CRC Mode.
FCCR (Flash CRC Control Register): 5056H
7
6
5
4
3
2
1
0
CRCMOD
CDCL
MDSEL
–
CKSEL2
CKSEL1
CKSEL0
CRCRUN
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Initial value: 00H
CRCMOD
Select CRC/Checksum Mode
0
Auto CRC/Checksum Mode
1
User CRC/Checksum Mode
CDCL
Flash CRC Data Register Clear
0
No effect
1
Clear Flash CRC Data register
NOTE)
1. This bit is set to ‘0’ automatically, after Flash CRC Data register is
cleared. FCDRH/L is cleared to “FFH”. Used only to User CRC Mode.
MDSEL
CRC/Checksum Selection
0
Select CRC
1
Select Checksum
CKSEL[2:0]
Select Flash CRC Clock
CKSEL2
CKSEL1
CKSEL0
Description
0
0
0
f
HFIRC
0
0
1
f
HFIRC
/2
0
1
0
f
HFIRC
/4
0
1
1
f
HFIRC
/8
1
0
0
f
X
(main system clock frequency)
Other values
Not used
CRCRUN
CRC/Checksum Start Signal & Busy Flag, Used only to Auto CRC/Checksum mode.
0
Indicates that CRC/Checksum operation is not running or has finished.
When written “0”, CRC/Checksum operation is finished by force even if
CRC/Checksum operation is running. It has no effect to write “0” if
CRC/Checksum is not running currently.
1
When written “1”, CRC/Checksum operation starts and this bit remains “1” as
long as CRC/Checksum operation is on-going. This bit is cleared to “0”
automatically after CRC/Checksum operation finishes.
NOTE)
1. If fHFIRC, fHFIRC/2, fHFIRC/4 and fHFIRC/8 is selected, HFIRCE must be cleared to ‘0’ at OSCCR.

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English