Abov MC96F8204 Series

173
MC96F8204
ABOV Semiconductor Co., Ltd.
Process
Description
Remarks
①
- No Operation
②
- 1st POR level Detection
- about 1.4V
③
- (INT-OSC 8MHz/8)x256x28h Delay section (=10ms)
- VDD input voltage must rise over than flash operating
voltage for Config read
- Slew Rate >= 0.05V/ms
④
- Config read point
- about 1.5V ~ 1.6V
- Config Value is determined by Writing Option
⑤
- Rising section to Reset Release Level
- 16ms point after POR or Ext_reset release
⑥
- Reset Release section (BIT overflow)
i) after16ms, after External Reset Release (External reset)
ii) 16ms point after POR (POR only)
- BIT is used for Peripheral stability
⑦
- Normal operation
Table 13.2 Boot Process Description