Abov MC96F8204 Series

176
MC96F8204
ABOV Semiconductor Co., Ltd.
Figure 13.11 Configuration timing when BOD RESET
VDD
Internal nPOR
PAD RESETB
BIT (for Config)
LVR_RESETB
BIT (for Reset)
INT-OSC 8MHz/8
INT-OSC (8MHz)
RESET_SYSB
Config Read
1us X 256 X 28h = about 10ms
1us X 4096 X 4h = about 16ms
F1
00
01
02
00
..
..
..
27
28
F1
“H”
INT-OSC 8MHz / 8 = 1MHz (1us)
“H”
“H”
Main OSC Off
01
02
03
04
00