Abov MC96F8204 Series

179
MC96F8204
ABOV Semiconductor Co., Ltd.
LVRCR (Low Voltage Reset Control Register) : D8H
7
6
5
4
3
2
1
0
LVRST
–
–
LVRVS3
LVRVS2
LVRVS1
LVRVS0
LVREN
R/W
–
–
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
LVRST
LVR Enable when Stop Release
0
Not effect at stop release
1
LVR enable at stop release
NOTE)
1. When this bit is ‘1’, the LVREN bit is cleared to ‘0’ by stop mode
release. (LVR enable)
2. When this bit is ‘0’, the LVREN bit is not effect by stop mode release.
LVRVS[3:0]
LVR Voltage Select
LVRVS3
LVRVS2
LVRVS1
LVRVS0
Description
0
0
0
0
1.60V
0
0
0
1
2.05V
0
0
1
0
2.15V
0
0
1
1
2.25V
0
1
0
0
2.37V
0
1
0
1
2.50V
0
1
1
0
2.65V
0
1
1
1
2.82V
1
0
0
0
3.01V
1
0
0
1
3.22V
1
0
1
0
3.47V
1
0
1
1
3.76V
1
1
0
0
4.10V
1
1
0
1
4.51V
Other Values
Not available
LVREN
LVR Operation
0
LVR Enable
1
LVR Disable
NOTE)
1. The LVRST, LVRVS[3:0] bits are cleared by a power-on reset but are retained by other reset signals.
2. The LVRVS[3:0] bits should be set to ‘0000b’ while LVREN bit is “1”.