Abov MC96F8204 Series User Manual

209
MC96F8204
ABOV Semiconductor Co., Ltd.
8.4.4 Extended SFR Map ................................................................................................................................... 54
8.4.5 SFR Map ................................................................................................................................................... 55
9 I/O Ports .................................................................................................................................................................. 57
9.1 I/O Ports ............................................................................................................................................................ 57
9.2 Port Register ..................................................................................................................................................... 57
9.2.1 Data Register (Px) ..................................................................................................................................... 57
9.2.2 Direction Register (PxIO) .......................................................................................................................... 57
9.2.3 Pull-up Resistor Selection Register (PxPU) .............................................................................................. 57
9.2.4 Open-drain Selection Register (PxOD) ..................................................................................................... 57
9.2.5 De-bounce Enable Register (P0DB) ......................................................................................................... 57
9.2.6 Port Function Selection Register (P0FSRH, P0FSRM, P0FSRL, P1FSR) ............................................... 57
9.2.7 Register Map ............................................................................................................................................. 58
9.3 P0 Port .............................................................................................................................................................. 59
9.3.1 P0 Port Description.................................................................................................................................... 59
9.3.2 Register description for P0 ........................................................................................................................ 59
9.4 P1 Port .............................................................................................................................................................. 64
9.4.1 P1 Port Description.................................................................................................................................... 64
9.4.2 Register description for P1 ........................................................................................................................ 64
9.5 P2 Port .............................................................................................................................................................. 66
9.5.1 P2 Port Description.................................................................................................................................... 66
9.5.2 Register description for P2 ........................................................................................................................ 66
10 Interrupt Controller ............................................................................................................................................ 67
10.1 Overview ........................................................................................................................................................... 67
10.2 External Interrupt .............................................................................................................................................. 69
10.3 Block Diagram .................................................................................................................................................. 70
10.4 Interrupt Vector Table ........................................................................................................................................ 71
10.5 Interrupt Sequence ........................................................................................................................................... 72
10.6 Effective Timing after Controlling Interrupt Bit .................................................................................................. 73
10.7 Multi Interrupt .................................................................................................................................................... 74
10.8 Interrupt Enable Accept Timing ......................................................................................................................... 75
10.9 Interrupt Service Routine Address .................................................................................................................... 75
10.10 Saving/Restore General-Purpose Registers ................................................................................................. 75
10.11 Interrupt Timing ............................................................................................................................................. 76
10.12 Interrupt Register Overview .......................................................................................................................... 77
10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3) .......................................................................................... 77
10.12.2 Interrupt Priority Register (IP, IP1) ......................................................................................................... 77
10.12.3 External Interrupt Flag Register (EIFLAG) ............................................................................................ 77
10.12.4 External Interrupt Polarity Register (EIPOL0, EIPOL1) ......................................................................... 77
10.12.5 Register Map .......................................................................................................................................... 77
10.12.6 Interrupt Register Description ................................................................................................................ 78
10.12.7 Register Description for Interrupt ........................................................................................................... 78
11 Peripheral Hardware .......................................................................................................................................... 83
11.1 Clock Generator ................................................................................................................................................ 83
11.1.1 Overview .................................................................................................................................................... 83
11.1.2 Block Diagram ........................................................................................................................................... 84
11.1.3 Register Map ............................................................................................................................................. 85
11.1.4 Clock Generator Register Description ....................................................................................................... 85
11.1.5 Register Description for Clock Generator ................................................................................................. 85
11.2 Basic Interval Timer .......................................................................................................................................... 88
11.2.1 Overview .................................................................................................................................................... 88
11.2.2 Block Diagram ........................................................................................................................................... 88
11.2.3 Register Map ............................................................................................................................................. 88
11.2.4 Basic Interval Timer Register Description ................................................................................................. 89
11.2.5 Register Description for Basic Interval Timer ............................................................................................ 89
11.3 Watch Dog Timer .............................................................................................................................................. 90
11.3.1 Overview .................................................................................................................................................... 90
11.3.2 WDT Interrupt Timing Waveform ............................................................................................................... 90
11.3.3 Block Diagram ........................................................................................................................................... 91

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English