Abov MC96F8204 Series User Manual

211
MC96F8204
ABOV Semiconductor Co., Ltd.
11.9.3 I2C Bit Transfer ........................................................................................................................................ 141
11.9.4 Start / Repeated Start / Stop ................................................................................................................... 141
11.9.5 Data Transfer ........................................................................................................................................... 142
11.9.6 I2C Acknowledge ..................................................................................................................................... 143
11.9.7 Synchronization / Arbitration .................................................................................................................... 144
11.9.8 Operation ................................................................................................................................................. 145
11.9.8.1 Master Transmitter ........................................................................................................................................... 145
11.9.8.2 Master Receiver .............................................................................................................................................. 147
11.9.8.3 I2C Slave Transmitter ...................................................................................................................................... 149
11.9.8.4 Slave Receiver ................................................................................................................................................ 150
11.9.9 Register Map ........................................................................................................................................... 151
11.9.10 I2C Register Description ...................................................................................................................... 151
11.9.11 Register Description for I2C ................................................................................................................. 152
11.10 FLASH CRC/Checksum Generator ............................................................................................................ 156
11.10.1 Overview .............................................................................................................................................. 156
11.10.1 Block Diagram ...................................................................................................................................... 161
11.10.2 Register Map ........................................................................................................................................ 161
11.10.3 Flash CRC Generator Register Description ........................................................................................ 162
11.10.4 Register Description for Flash CRC Generator ................................................................................... 162
12 Power Down Operation .................................................................................................................................... 165
12.1 Overview ......................................................................................................................................................... 165
12.2 Peripheral Operation in IDLE/STOP Mode ..................................................................................................... 165
12.3 IDLE Mode ...................................................................................................................................................... 166
12.4 STOP Mode .................................................................................................................................................... 167
12.5 Release Operation of STOP Mode ................................................................................................................. 168
12.6 Register Map .................................................................................................................................................. 169
12.7 Power Down Operation Register Description ................................................................................................. 169
12.8 Register Description for Power Down Operation ............................................................................................ 169
13 RESET................................................................................................................................................................ 170
13.1 Overview ......................................................................................................................................................... 170
13.2 Reset Source .................................................................................................................................................. 170
13.3 RESET Block Diagram ................................................................................................................................... 170
13.4 RESET Noise Canceller ................................................................................................................................. 171
13.5 Power on RESET ............................................................................................................................................ 171
13.6 External RESETB Input .................................................................................................................................. 174
13.7 Brown Out Detector Processor ....................................................................................................................... 175
13.8 LVI Block Diagram .......................................................................................................................................... 177
13.9 Register Map .................................................................................................................................................. 177
13.10 Reset Operation Register Description ........................................................................................................ 177
13.11 Register Description for Reset Operation ................................................................................................... 178
14 On-chip Debug System .................................................................................................................................... 181
14.1 Overview ......................................................................................................................................................... 181
14.1.1 Description ............................................................................................................................................... 181
14.1.2 Feature .................................................................................................................................................... 182
14.2 Two-Pin External Interface.............................................................................................................................. 183
14.2.1 Basic Transmission Packet ..................................................................................................................... 183
14.2.2 Packet Transmission Timing .................................................................................................................... 184
14.2.2.1 Data Transfer ................................................................................................................................................... 184
14.2.2.2 Bit Transfer ...................................................................................................................................................... 184
14.2.2.3 Start and Stop Condition .................................................................................................................................. 185
14.2.2.4 Acknowledge Bit .............................................................................................................................................. 185
14.2.3 Connection of Transmission .................................................................................................................... 186
15 Flash Memory ................................................................................................................................................... 187
15.1 Overview ......................................................................................................................................................... 187
15.1.1 Description ............................................................................................................................................... 187
15.1.2 Flash Program ROM Structure ................................................................................................................ 188
15.1.3 Register Map ........................................................................................................................................... 189
15.1.4 Register Description for Flash Memory Control and Status .................................................................... 189

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English