Abov MC96F8204 Series User Manual

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MC96F8204
ABOV Semiconductor Co., Ltd.
P0DB (P0 Debounce Enable Register) : 95H
7
6
5
4
3
2
1
0
DBCLK1
DBCLK0
–
P04DB
P03DB
P02DB
P01DB
P00DB
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
DBCLK[1:0]
Configure Debounce Clock of Port
DBCLK1
DBCLK0
Description
0
0
fx/1
0
1
fx/4
1
0
fx/32
1
1
fx/4096
P04DB
Configure Debounce of P04 Port
0
Disable
1
Enable
P03DB
Configure Debounce of P03 Port
0
Disable
1
Enable
P02DB
Configure Debounce of P02 Port
0
Disable
1
Enable
P01DB
Configure Debounce of P01 Port
0
Disable
1
Enable
P00DB
Configure Debounce of P00 Port
0
Disable
1
Enable
NOTE)
1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the
signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode release.

Abov MC96F8204 Series Specifications

General

Brand	Abov
Model	MC96F8204 Series
Category	Microcontrollers
Language	English