Section 8 Status Structure
8-4
The status model uses an IEEE 488.1 status byte. This status byte consists of
seven summary message bits provided by the status data structure. To generate
these summary message bits, the status data structure is comprised of two mod-
els: a register model and a queue model.
Register model A pair of registers used to record an event that a device has encountered and a
condition. It consists of an event status register and an event status enable regis-
ter. When the results of ANDing the values of bits of these registers is not 0, the
corresponding status register bits are set to 1s. In other cases, the corresponding
status register bits are set to 0s. If the result of ORing the values of status register
bits is 1, the summary message bit is set to 1. If the result of ORing these bits is 0,
the summary message bit is set to 0.
Queue model A data structure in which status values or information are removed in the same
order they were entered. Only when the queue structure contains data, the corre-
sponding bit is set to 1. If it is empty, the corresponding bit is set to 0.
Based on the concept of the above register model and queue model, the IEEE
488.2 standard status model is constructed from two types of register models and
a queue model.
(a) Standard event status register and standard event status enable register
(b) Status byte register and service request enable register
(c) Output queue
Standard Event Status Register This register has the register model structure mentioned above. It has eight bits
corresponding to eight standard events encountered by the device: (1) power on,
(2) user request, (3) command error, (4) execution error, (5) device dependent
error, (6) query error, (7) bus control request, (8) operation complete. The result
of logical OR is output to the status byte register bit 5 (DIO 4) as an event status
bit (ESB) summary message.
Status Byte Register The status byte register consists of an RQS bit and seven summary message bits
for setting status summary messages from the status data structure. It is used in
combination with a service request enable register. When the result of ORing the
values of these two registers is 0, the SRQ is set ON. In this case, the status byte
register bit "DIO 7" is reserved by the system as an RSQ bit, so this bit indicates
to an external controller that a service request exists. The function of the SRQ
conforms to IEEE 488.1.
Output Queue This queue has the queue model structure mentioned above. Its contents are sum-
marized and transferred to the status byte register bit 4 (DIO 5) as a message
available (MAV) summary message.
To Next Page
Loading...
Need help?
General
